search

CommonEvaluationPlatform / CEP

The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely available components.
BSD 3-Clause "New" or "Revised" License
21 stars 7 forks source link

Verilator bareMetal test VCD is incomplete in CEP v4.5 and v4.7 #41

Open jordankrim opened 2 months ago

jordankrim commented 2 months ago

I was able to de-cipher (perhaps?) through looking to the sims/verilator/Makefile how to create a VCD when running Verilator in v4.5 going forward. The documentation as far as can tell has never been updated from CEP 4.4 where one can just add -v to the command line without having to compile with "debug", but in 4.5 going forward apparently one has to compile with "debug". The problem is the VCD appears to just stop after a short time when running a bareMetal test and is therefore not showing the entire timespan of the sim.

This is how I compiled the Verilated code:

make SUB_PROJECT=cep_verilator debug

Then I ran this:

./simulator-chipyard.harness-CEPVerilatorRocketConfig-debug -vcdfile=../../sims/cep_cosim/testSuites/bareMetalTests/macro4Mix/macro4Mix.vcd ../../sims/cep_cosim/testSuites/bareMetalTests/macro4Mix/riscv_wrapper.elf +loadmem=../../sims/cep_cosim/testSuites/bareMetalTests/macro4Mix/riscv_wrapper.hex +loadmem_addr=80000000 cep_playback: playback command sequence totalCmds=212 cep_playback: playback command sequence totalCmds=212 Test Passed [UART] UART0 is here (stdin/stdout).

In the Makefile I see +vcdfile but in my invocation I have to user -vcdfile=.. otherwise I get an invalid parameter message. Why is it -vcdfile instead of +vcdfile?

Here is the size of the VCD is this in v4.7 which is incomplete:

-rw-rw-r-- 1 jkrim jkrim 6893742 Sep 23 10:31 ./cep_cosim/testSuites/bareMetalTests/macro4Mix/macro4Mix.vcd

In CEP v4.4 a full simulation VCD that is working with the correct size is:

-rw-rw-r-- 1 jkrim jkrim 2763928869 Sep 23 10:40 ../../sims/cep_cosim/testSuites/bareMetalTests/macro4Mix/macro4Mix.vcd

Any idea why is it being "truncated" (or stopping short of the simulation end time?) in V4.7?

jordankrim commented 2 months ago

It appears that the order of the plusargs makes a difference. I don't know why this is the case. The VCD one has to be last.

This works in both CEP v4.5 and v4.7 vs. what I showed previously:

./simulator-chipyard.harness-CEPVerilatorRocketConfig-debug ../../sims/cep_cosim/testSuites/bareMetalTests/macro4Mix/riscv_wrapper.elf +loadmem=../../sims/cep_cosim/testSuites/bareMetalTests/macro4Mix/riscv_wrapper.hex +loadmem_addr=80000000 +vcdfile=../../sims/cep_cosim/testSuites/bareMetalTests/macro4Mix/macro4Mix.vcd

But, there is still a problem where CEP v4.5 doesn't print any of the "normal" cep_playback messages but creates the proper sized VCD as this:

./simulator-chipyard.harness-CEPVerilatorRocketConfig-debug ../../sims/cep_cosim/testSuites/bareMetalTests/macro4Mix/riscv_wrapper.elf +loadmem=../../sims/cep_cosim/testSuites/bareMetalTests/macro4Mix/riscv_wrapper.hex +loadmem_addr=80000000 +vcdfile=../../sims/cep_cosim/testSuites/bareMetalTests/macro4Mix/macro4Mix.vcd [UART] UART0 is here (stdin/stdout).

But in CEP v4.7 this is printed to the screen:

./simulator-chipyard.harness-CEPVerilatorRocketConfig-debug ../../sims/cep_cosim/testSuites/bareMetalTests/macro4Mix/riscv_wrapper.elf +loadmem=../../sims/cep_cosim/testSuites/bareMetalTests/macro4Mix/riscv_wrapper.hex +loadmem_addr=80000000 +vcdfile=../../sims/cep_cosim/testSuites/bareMetalTests/macro4Mix/macro4Mix.vcd cep_playback: playback command sequence totalCmds=212 cep_playback: playback command sequence totalCmds=212 Test Passed [UART] UART0 is here (stdin/stdout).

Any idea why CEP 4.5 prints are gone with debug (to dump a VCD)?

jordankrim commented 1 month ago

OK. The prints are not gone. They disappear if the last thing done was run the Xcelium bareMetal tests. If one wants to back to the Verilator tests one has to re-compile all the baremetal tests for Verilator (which uses libgloss) and then the prints will work.