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EPFL-LAP / dynamatic

DHLS (Dynamic High-Level Synthesis) compiler based on MLIR
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[Verilog] Control merge Verilog module not synthesizable #149

Open Jiahui17 opened 2 months ago

Jiahui17 commented 2 months ago

Commit: d47c079

To reproduce the issue, use the following frontend script:

set-dynamatic-path ./dynamatic;   set-src ./dynamatic/integration-test/fir/fir.c;   set-clock-period 4;   compile  ;   write-hdl --hdl verilog;   simulate;   synthesize;   exit

Behavior:

[INFO] Launching Vivado synthesis
ERROR: [Synth 8-3380] loop condition does not converge after 2000 iterations [/home/jxu/Repositories/dhls-utils/dynamatic/integration-test/fir/out/synth/hdl/control_merge_dataless.v:28]
ERROR: [Synth 8-6156] failed synthesizing module 'control_merge_dataless' [/home/jxu/Repositories/dhls-utils/dynamatic/integration-test/fir/out/synth/hdl/control_merge_dataless.v:2]
ERROR: [Synth 8-6156] failed synthesizing module 'fir' [/home/jxu/Repositories/dhls-utils/dynamatic/integration-test/fir/out/synth/hdl/fir.v:1]
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
[INFO] Logic synthesis succeeded

The statement that breaks the for loop works in modelsim but not in vivado. https://github.com/EPFL-LAP/dynamatic/blob/d47c0796db1b9e5a775a168eca9b916d5b31860d/data/verilog/handshake/dataless/control_merge.v#L24-L34