Open sumdudelr opened 1 week ago
The included "addsub" block's YAML definition contains a string parameter. The quotation marks do not carry forward to the generated rfnoc_image_core.sv. Building FPGA image will fail.
rfnoc_image_core.sv
FPGA image builds successfully
Synthesis fails with:
ERROR: [Synth 8-1031] Verilog is not declared [repo/icores/build-x310_rfnoc_image_core/rfnoc_image_core.sv:1591]
Just add an "addsub" block to your RFNoC image.
Can be fixed by adding a few lines to addsub.yml to use hdl_parameters as is done in OOT example gain.yml.
addsub.yml
hdl_parameters
gain.yml
Issue Description
The included "addsub" block's YAML definition contains a string parameter. The quotation marks do not carry forward to the generated
rfnoc_image_core.sv. Building FPGA image will fail.Setup Details
Expected Behavior
FPGA image builds successfully
Actual Behaviour
Synthesis fails with:
Steps to reproduce the problem
Just add an "addsub" block to your RFNoC image.
Additional Information
Can be fixed by adding a few lines to
addsub.ymlto usehdl_parametersas is done in OOT examplegain.yml.