Ponq can't write bin files to fpga0/firmware

[alexisduhamel]

Hello,

I'm trying to make FOS working on my board since I have neither the ultra96, zcu102 nor the ultrazed. However I fail to write my bin files to /sys/class/fpga_manager/fpga0/firmware.

Since the project relies on PYNQ libraries, I'm using a PYNQ-Z2 board with Xilinx's pre-compiled Pynq 2.3 SD card image (version choice based on compatibilities with FOS).

So far, those were my steps:

1. Load SD card image and boot the pynq board.
2. Clone the FOS repository on the board
3. apt update/upgrade and run fos/install.sh
4. In fos/udmalib/udmabuf, execute make
5. install the compiled kernel module with fos/udmalib/setupUdma.sh

I then created a Vivado 2018.2 static project that consists of a Zynq PS communicating with a AXIS FIFO in PL via DMA (this project has already been tested with the PYNQ Overlay libraries and works just fine). The bitstream has been generated without compression nor encryption.

I used the template accelerator json files from your tutorial to create my own. I had to write a repo.json and a shell json files as the Ponq library kept asking for it. The following code has been working so far as the bin files has been copied to the relevant bin folder, but the last line from the python code always fail:

repo.json

{
  "shell": "PYNQ_Z2",
  "accelerators": [
    "static_full_vadd"
  ]
}

static_full_add.json

{
  "name": "static_full_add",
  "address": "0x40400000",
  "bitfiles": [
    {"name": "static_full_vadd.bit", "region": "full"}
  ],
  "registers":[
    {"name":"MM2S_DMACR", "offset":"0x0"},
    {"name":"MM2S_DMASR", "offset":"0x4"},
    {"name":"MM2S_CURDESC", "offset":"0x8"},
    {"name":"MM2S_CURDESC_MSB", "offset":"0xC"},
    {"name":"MM2S_TAILDESC", "offset":"0x10"},
    {"name":"MM2S_TAILDESC_MSB", "offset":"0x14"},
    {"name":"SG_CTL", "offset":"0x2C"},
    {"name":"S2MM_DMACR", "offset":"0x30"},
    {"name":"S2MM_DMASR", "offset":"0x34"},
    {"name":"S2MM_CURDESC", "offset":"0x38"},
    {"name":"S2MM_CURDESC_MSB", "offset":"0x3C"},
    {"name":"S2MM_TAILDESC", "offset":"0x40"},
    {"name":"S2MM_TAILDESC_MSB", "offset":"0x44"}
  ]
}

PYNQ_Z2.json

{
  "name": "PYNQ_Z2",
  "bitfile": "static_full_vadd.bin",
  "regions": [
    {"name": "full", "blank": "static_full_vadd.bin", "bridge": "0x4040FFFF", "addr": "0x40400000"}
  ]
}

# Jupyter Notebook Python code
# Loading dependencies
import mmap, os, random, time, numpy as np
from ponq import Ponq

# Initialising Ponq bitstream repository
manager = Ponq(repository="./bitstreams")
acc = manager.load("static_full_vadd")

The ponq library fails to load the binary file as I get the following error: OSError: [Errno 22] Invalid argument.

The /sys/class/fpga_manager/fpga0/firmware exists and all users have write access on it. I am not able to echo the bin file in fpga0/firmware though (echo: write error: invalid argument). The Pynq overlay PCAP manager works fine however.

Do you have any fix or pointer to help me out?

Have a good day,

Alexis.

[khoapham]

Hi @alexisduhamel ,

Thanks for letting us know about the issue! How did you obtain the bitstream (.bit and .bin files)? Did you get them from Vivado or from our FOS compilation flow?

It seems like the FPGA manager (fpga0/firmware) couldn't recognise the format of the bin file you put in. For more info how to use FPGA manager and generate a valid bin file, please see the below Xilinx page!

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841645/Solution+Zynq+PL+Programming+With+FPGA+Manager

Note that: the "bootgen" command can be found in either PetaLinux or Vitis/Vivado SDK package.

If further issue or question, please let use know!

Kind regards, Khoa

[alexisduhamel]

First of all, thank you for the very quick reply :)

Are you mentionning the FOS compilation flow for static HLS accelerator? If so I followed this tutorial without the HLS part, my "IP" is a simple AXIS FIFO instead.

The .bit file was obtained through the Vivado 2018.2 flow. The .bin file has been generated via bootgen in Xilinx SDK Bootgen GUI (Xilinx > Create Bootgen) which executed the bootgen command in the Vivado console. As much as I would have loved the bin file to be the culprit, I don't think it is.

Looking at your Wiki link, I see there are some kernel configurations steps. As I'm using precompiled sd card images because I'm unable to compile a kernel myself (company policy with admin rights and licence use), can you please confirm this wouldn't create problems down the line?

[khoapham]

Hi,

The SDK Bootgen GUI may not be passing the right arguments to the command in order to generate a proper bin file. Please use the Vivado SDK/Vitis Shell and follow the instructions in the Xilinx link to generate that bin file! The Vivado SDK/Vitis Shell can be found as in the below photo:

Otherwise, a PetaLinux console should work as well.

You should be able to manually echo the bin file to the FPGA manager (fpga0/firmware) before using PONG for the automatic bitstream loading.

As long as the Pynq overlay PCAP manager works, the kernel configurations should be fine.

Kind regards, Khoa

[alexisduhamel]

Hi,

So I generated the bitstream once again to start with a clean slate.

After having tested the .bit and .hwh files with Pynq Overlay, I ran the following command with the Vivado SDK shell (note: pynq z2 is not arch zynqmp):

bootgen -image bitstream.bif -arch zynq -o bitstream.bin -w

after having created the bitstream.bif file:

all:
{
        design_1_wrapper.bit /* Bitstream file name */
}

Vivado GUI missed the "-w" option compared to inline. The .bin file has been generated successfully, however fpga0/firmware still times out with echo (consequently ponq fails too).

[khoapham]

Hi,

Sorry, are we looking at the same document? I meant the below "-process_bitstream bin" arguments should be put in the "bootgen" command:

As far as I know, a valid bin file to FPGA Manager will have the bit file byte-swapped, while other normal bin files won't. I recall the Pynq Overlay does the same thing to a bit file (a.k.a byte-swapped bit file = bin file), when I looked at the Pynq's Python code.

Good luck this time!

Khoa

[khoapham]

Hi,

Sorry, I tested both commands on Vitis 2019.2 and they both generated byte-swapped bin files.

bootgen -image bitstream.bif -arch zynq -process_bitstream bin

bootgen -image bitstream.bif -arch zynq -o bitstream.bin -w

However, the command without "-process_bitstream bin" argument generated more metadata in the header of the bin file, which may not be able to be processed by the FPGA Manager.

Unable to test on the board as I don't have any Pynq-Z2 at the moment.

If any issue or question, please let me know!

Kind regards, Khoa

[alexisduhamel]

Hi,

I was looking at the steps from the HLS compilation flow.

So as you mentionned the -o one generated more metadata, and the -process_bitstream creates a slightly lighter file. I'm now able to echo this bin file in fpga0/firmware, even though I don't have any output from the Xilinx Zynq FPGA Manager as shown in the Wiki. I think that's a clue that I need to investigate in the meantime.

Kind regards, Alexis

[khoapham]

Hi,

If the FPGA Manager doesn't inform an error, probably the bitstream went through. You may make a simple driver to query to the IP if the FPGA was reprogrammed successfully.

The HLS compilation flow requires a static system and compatibles templates for reconfigurable modules, which are not available now for Pynq-Z2 platform.

[alexisduhamel]

Hi,

I confirm I was able to program the FPGA this way.

Thank you kindly for the help. Looking forward to try the project.

Alexis