Lint error when using ICE40 primitives

[zapta]

I have a verilog module that uses an ICE40 SB_IO built in primitive (see below). When running apio lint I get the error below. Does apio provide a way to fix or suppress that error? For example, suppressing lint in that file, or providing the path to the library with the SB_IO definition.

If there is no solution, or a workaround, we should make this issue a feature request.

Error log:

$ apio lint
Loading custom boards.json from project dir
verilator --lint-only --timing -Wno-TIMESCALEMOD -Wno-MULTITOP ftdi_tx.v i2s_rx.v i2s_test_pattern.v i2s_timing.v lcd_i2c.v lcd_i2c_io.v leds.v main.v queue.v queue_pusher.v register.v reset_gen.v ftdi_tx_tb.v i2s_rx_tb.v i2s_timing_tb.v lcd_i2c_tb.v leds_tb.v main_tb.v queue_pusher_tb.v queue_tb.v register_tb.v reset_gen_tb.v
%Error: lcd_i2c_io.v:9:3: Cannot find file containing module: 'SB_IO'
9 |   SB_IO #(
|   ^~~~~
%Error: lcd_i2c_io.v:9:3: This may be because there's no search path specified with -I<dir>.
9 |   SB_IO #(
|   ^~~~~
... Looked in:
SB_IO
SB_IO.v
SB_IO.sv
obj_dir/SB_IO
obj_dir/SB_IO.v
obj_dir/SB_IO.sv
%Error: Exiting due to 2 error(s)
scons: *** [hardware] Error 1

Verilog module that uses SB_IO:

module lcd_i2c_io (
    input  i2c_tx_data,
    output i2c_rx_data,
    inout  i2c_data_pin
);

  SB_IO #(
      .PIN_TYPE(6'b101001),
      .PULLUP  (1)
  ) data_pin[0:0] (
      .PACKAGE_PIN({i2c_data_pin}),
      .OUTPUT_ENABLE({!i2c_tx_data}),
      .D_OUT_0(1'b0),
      .D_IN_0({i2c_rx_data})
  );

endmodule

[zapta]

Do we need to add this library file to the verilator command?

~/.apio/packages/tools-oss-cad-suite/share/yosys/ice40/cells_sim.v

Original repo: https://github.com/YosysHQ/yosys/blob/main/techlibs/ice40/cells_sim.v

[zapta]

It seems that the yosys library file need to be to the verilator command in order to provide the SB_IO definition. However, that library file has lint errors on its own

 $ verilator --lint-only   ~/.apio/packages/tools-oss-cad-suite/share/yosys/ice40/cells_sim.v
%Error: /Users/user/.apio/packages/tools-oss-cad-suite/share/yosys/ice40/cells_sim.v:1497:21: syntax error, unexpected '=', expecting ','
 1497 |  input  [15:0] MASK = 16'h 0000,
      |                     ^
%Error: /Users/user/.apio/packages/tools-oss-cad-suite/share/yosys/ice40/cells_sim.v:1533:2: syntax error, unexpected generate
 1533 |  generate
      |  ^~~~~~~~
%Error: /Users/user/.apio/packages/tools-oss-cad-suite/share/yosys/ice40/cells_sim.v:1607:2: syntax error, unexpected initial
 1607 |  initial begin
      |  ^~~~~~~
%Error: /Users/user/.apio/packages/tools-oss-cad-suite/share/yosys/ice40/cells_sim.v:1736:21: syntax error, unexpected '=', expecting ','
 1736 |  input  [15:0] MASK = 16'h 0000,
      |                     ^
%Error: /Users/user/.apio/packages/tools-oss-cad-suite/share/yosys/ice40/cells_sim.v:1761:2: syntax error, unexpected IDENTIFIER
 1761 |  SB_RAM40_4K #(
      |  ^~~~~~~~~~~
%Error: /Users/user/.apio/packages/tools-oss-cad-suite/share/yosys/ice40/cells_sim.v:1872:21: syntax error, unexpected '=', expecting ','
 1872 |  input  [15:0] MASK = 16'h 0000,
      |                     ^
%Error: /Users/user/.apio/packages/tools-oss-cad-suite/share/yosys/ice40/cells_sim.v:1897:2: syntax error, unexpected IDENTIFIER
 1897 |  SB_RAM40_4K #(
      |  ^~~~~~~~~~~
%Error: /Users/user/.apio/packages/tools-oss-cad-suite/share/yosys/ice40/cells_sim.v:2008:21: syntax error, unexpected '=', expecting ','
 2008 |  input  [15:0] MASK = 16'h 0000,
      |                     ^
%Error: /Users/user/.apio/packages/tools-oss-cad-suite/share/yosys/ice40/cells_sim.v:2033:2: syntax error, unexpected IDENTIFIER
 2033 |  SB_RAM40_4K #(
      |  ^~~~~~~~~~~
%Error: Exiting due to 9 error(s)

[zapta]

Here is something that seems to worked for me. Need to be implemented. This is for the ice40, i presume it's similar for the other architectures.

1. Add to the verilator command:

--bbox-unsup -DNO_ICE40_DEFAULT_ASSIGNMENTS verilator.vlt <yosys-path>/share/yosys/ice40/cells_sim.v

3. Add a scons target that creates the file verilator.vlt with the text:

`verilator_config
lint_off -rule COMBDLY      -file "*/yosys/ice40/cells_sim.v"
lint_off -rule WIDTHEXPAND  -file "*/yosys/ice40/cells_sim.v"

EDIT: It's possible that the -D flag will not be necessary with newer version of verilator. Per https://github.com/verilator/verilator/issues/5440.