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FPGAwars / apio

:seedling: Open source ecosystem for open FPGA boards
https://github.com/FPGAwars/apio/wiki
GNU General Public License v2.0
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[Feature Request] Time analysis for the ECP5 and Gowin families. #432

Open zapta opened 3 days ago

zapta commented 3 days ago

Currently apio time is not implemented for the ECP5 and Gowin families. This issue is for implementing them.

Timing verification is important to confirm that the synthesized code is within the FPGA spec.

If there is a wroaround that provides some time verification for ECP5 Gowin, please post them here, so they can be added to the help text of the apio time command.

zapta commented 3 days ago

nextpnr seems to check the timing condition (with 12Mhz as the default target speed).

repo/test-examples/ColorLight-5A-75B-V8/Blinky $ nextpnr-ecp5 --25k --package CABGA256 --json hardware.json --textcfg hardware.config --lpf pinout.lpf -q --timing-allow-fail --force --freq 400
Warning: Max frequency for clock '$glbnet$CLK$TRELLIS_IO_IN': 295.42 MHz (FAIL at 400.00 MHz)
1 warning, 0 errors

It also seems to log the actual speed when run in verbose mode.

Would be useful to add to apio.ini a field with the target frequency, with fallback to the board specification in boards.json.