aflynn
commented
4 years ago I'm not sure about the file version.
What actually got fabricated was what I was trying to explain in my previous email ... nothing was "plugged with epoxy". That is, the Thru (unplugged) vias in the first rev were replaced, I believe, by stacked vias. When you have stacked vias in the "thin copper foil process", the L1-L2 via automatically gets plated ... i.e. filled with copper (not plugged with epoxy and plated over). In the "thin copper foil process" required for the fine-feature etching, the dielectric between L1 and L2 is required to be the thinness required for blind vias so that the plating step by itself will fill the L1-L2 via with copper.
On Fri, Jun 5, 2020 at 1:07 PM Gregory Wright notifications@github.com wrote:
@kostatro https://github.com/kostatro @aflynn https://github.com/aflynn Does the Altium database from the BWRC reflect the final state of the board as manufacturer by Sierra, or did Sierra make changes that were not backported to the BWRC?
The question came up because it appears as if there are thru vias under the IC even in the file fader2_blind_vias_pcb.PcbDoc. My understanding is that these were plugged so that the under-chip bump attach points would be flat.
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gwright83
kostatro
caolen
@kostatro @aflynn Does the Altium database from the BWRC reflect the final state of the board as manufacturer by Sierra, or did Sierra make changes that were not backported to the BWRC?
The question came up because it appears as if there are thru vias under the IC even in the file fader2_blind_vias_pcb.PcbDoc. My understanding is that these were plugged so that the under-chip bump attach points would be flat.