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HFF-Git / VCPU-32

This is a vintage design CPU with 32-bits. See the document in the VCPU-32-Documentation folder for a more detailed description.
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mnemonic in document does not match instruction #11

Closed wesch closed 3 months ago

wesch commented 3 months ago

at following instructions the mnemonic in document does not match instruction format
where is segment register?

LD [.M] r, ofs(b)
LDO r, operand
LDPA r, a(b)
LDR r, ofs(b)
PRB [.] r, operand STw [.M] operand, r STC operand r

HFF-Git commented 3 months ago

Hallo Wolfgang,

Die Instruktionen haben ein „seg“ field.

LD [.M] r, ofs(b).

LDPA r, a(b)

LDR r, ofs(b)

PRB [.] r, operand

STw [.M] operand, r

STC operand r

Im Document:

-> the „seg“ field ( Bits 12, 13 ) selects the segment register. A value of zero selects implicit among SR4 to SR7, a value of 1 to 3 selects SR1 to SR3.

LDO r, operand

-> the is no segment in the LDO instruction.

Viele Grüsse, Helmut

Am 03.06.2024 um 17:54 schrieb WolfgangE @.***>:

at following instructions the mnemonic in document does not match instruction format where is segment register?

LD [.M] r, ofs(b) LDO r, operand LDPA r, a(b) LDR r, ofs(b) PRB [.] r, operand STw [.M] operand, r STC operand r

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wesch commented 3 months ago

Ja, aber wo ist das seg-Feld im mnemonic benannt?Am 03.06.2024 um 18:21 schrieb Helmut Fieres @.***>: Hallo Wolfgang,

Die Instruktionen haben ein „seg“ field.

LD [.M] r, ofs(b).

LDPA r, a(b)

LDR r, ofs(b)

PRB [.] r, operand

STw [.M] operand, r

STC operand r

Im Document:

-> the „seg“ field ( Bits 12, 13 ) selects the segment register. A value of zero selects implicit among SR4 to SR7, a value of 1 to 3 selects SR1 to SR3.

LDO r, operand

-> the is no segment in the LDO instruction.

Viele Grüsse, Helmut

Am 03.06.2024 um 17:54 schrieb WolfgangE @.***>:

at following instructions the mnemonic in document does not match instruction format

where is segment register?

LD [.M] r, ofs(b)

LDO r, operand

LDPA r, a(b)

LDR r, ofs(b)

PRB [.] r, operand

STw [.M] operand, r

STC operand r

—

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HFF-Git commented 3 months ago

Das gehört in die Klammer, wenn SR1 bis SR3 gewünscht wird…. Ich addiere es …

Am 03.06.2024 um 19:03 schrieb WolfgangE @.***>:

Ja, aber wo ist das seg-Feld im mnemonic benannt?Am 03.06.2024 um 18:21 schrieb Helmut Fieres @.***>: Hallo Wolfgang,

Die Instruktionen haben ein „seg“ field.

LD [.M] r, ofs(b).

LDPA r, a(b)

LDR r, ofs(b)

PRB [.] r, operand

STw [.M] operand, r

STC operand r

Im Document:

-> the „seg“ field ( Bits 12, 13 ) selects the segment register. A value of zero selects implicit among SR4 to SR7, a value of 1 to 3 selects SR1 to SR3.

LDO r, operand

-> the is no segment in the LDO instruction.

Viele Grüsse, Helmut

Am 03.06.2024 um 17:54 schrieb WolfgangE @.***>:

at following instructions the mnemonic in document does not match instruction format

where is segment register?

LD [.M] r, ofs(b)

LDO r, operand

LDPA r, a(b)

LDR r, ofs(b)

PRB [.] r, operand

STw [.M] operand, r

STC operand r

—

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HFF-Git commented 3 months ago

Added clarification to document.