Addition of a comprehensive top-level verification environment for the design.
The steps to be followed:
1) Make a diagram of this verification environment indicating the placement of components including dummy main memory, dummy cpu, interconnect, dummy caches, drivers for inputs and monitors for outputs.
2) Implementation of this in system Verilog.
3) Make sure basic read and write requests are performed accurately i.e: Correct data is being read from and written to main memory, cpu and dummy caches.
4) If any problem is faced regarding the 3 modules(cache datapath, cache controller and ace controller), create an issue regarding that. The issue will be assigned to the group member who worked on that module.
Addition of a comprehensive top-level verification environment for the design. The steps to be followed: 1) Make a diagram of this verification environment indicating the placement of components including dummy main memory, dummy cpu, interconnect, dummy caches, drivers for inputs and monitors for outputs. 2) Implementation of this in system Verilog. 3) Make sure basic read and write requests are performed accurately i.e: Correct data is being read from and written to main memory, cpu and dummy caches. 4) If any problem is faced regarding the 3 modules(cache datapath, cache controller and ace controller), create an issue regarding that. The issue will be assigned to the group member who worked on that module.