Create a script to check and force every port to have one of the following suffixes _i, _o, _io, _m, _s.
Note, the _io port suffix is not the same as the _io signal suffix.
The _io port suffix means that the port contains various signals of different types (inputs and outputs or inouts).
The _io signal suffix means that the signal is of type inout in verilog.
Some ports of lib modules and ports of
csrsdo not have any suffix in their name. Example: https://github.com/IObundle/py2hwsw/blob/main/py2hwsw/lib/hardware/fifo/iob_fifo_sync/iob_fifo_sync.py#L104Create a script to check and force every port to have one of the following suffixes
_i,_o,_io,_m,_s.Note, the
_ioport suffix is not the same as the_iosignal suffix. The_ioport suffix means that the port contains various signals of different types (inputs and outputs or inouts). The_iosignal suffix means that the signal is of typeinoutin verilog.