Create FIFO-like comb. only single cycle handshake wire/clock crossing

JulianKemmerer / PipelineC

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

https://github.com/JulianKemmerer/PipelineC/wiki

GNU General Public License v3.0

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Create FIFO-like comb. only single cycle handshake wire/clock crossing #83

Open JulianKemmerer opened 2 years ago

JulianKemmerer commented 2 years ago

Similar to how async clock crossings have a FIFO interface with valid/not empty/write+ready/not full signals... do same thing for a "~0 element fifo" same clock domain data transfer. Just becomes a handshaking mechanism for moving data between func (as opposed to plain, unidirectional, non flow-control wires).

JulianKemmerer commented 2 years ago

Should be good for (FSM style arbitration, or not) sharing of N resources among M users.