Multiple core increases parse errors

[laser-vectrix]

I'm using can2040 on one core and a wifi (lwip_threadsafe_background) on the 2nd core. CANBus data is being replayed on a TCP connection. At 250kbit/s (with a message every 4ms) I get around 0.5% CAN parse errors when TCP connections are running (comparing to near 0 when they are not), I guess that is due to PIO interrupts being handled on the 2nd core in which the cyw43 and lwip are being used.

If this could be the case, is there anyway to force PIO IRQs to being handled in a given core?

    // Enable irqs
    irq_set_exclusive_handler(PIO0_IRQ_0_IRQn, PIOx_IRQHandler);
    NVIC_SetPriority(PIO0_IRQ_0_IRQn, 1);
    NVIC_EnableIRQ(PIO0_IRQ_0_IRQn);

[KevinOConnor]

To the best of my knowledge, running that code on core0 sets the interrupts for core0, and running that code on core1 sets the interrupts for core1. (That is, those functions typically alter registers in a memory space that is private to each core.) However, the technical details like that could vary from build system to build system, so best to check the documentation for the core libraries you are using.

In addition to the processing load on each arm core, be aware that flash access can result in processing stalls. It may be necessary to load the application into ram (or at least, load the can2040 interrupt handling code into ram) in order to get predictable processing time. (Loading an application into ram is heavily dependent on the build environment though - see #18 ).

Cheers, -Kevin

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