MEGA65 / mega65-core

MEGA65 FPGA core
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Vertical de-jitter of port 1 broken #828

Closed ki-bo closed 2 months ago

ki-bo commented 2 months ago

Core 0.96

Attaching a 1351 mouse to either port, the POT lines should only jitter in bit 0, but with a MEGA65 core, they jitter in both bits 0 and 1. Using the same hardware with C64 core shows the expected jitter. The problem is that most mouse driver implementations don't expect jitter in bit 1 and behave very unstable in their movements. Some implementations (like BASIC65 MOUSE ON) use a special way to handle old sampled values that are remembered, but those just work due to limiting themselves to a lower resolution which should not be the case.

Use this test program on a C64 core and the MEGA65 core to reproduce:

10 X=PEEK(54297) AND 254 : Y=PEEK(54298) AND 254
20 PRINT X,Y : GOTO 10

On C64 core, the printed numbers stay stable. On MEGA65, they jitter quite a lot. This is not just related to BASIC, but also is reproducible if the values are read with a machine language program.

IMG_2433 IMG_2432

ki-bo commented 2 months ago

The jitter is indeed in bit0 (expected) and in bit1 (unexpected). There is a de-jitter function in the core that can eliminate the bit1 jitter, thus making the mouse usable for regular mouse driver implementations known from the C64. This had an issue with vertical movements in port 1, which was just a copy/paste error in the VHDL. The above commit fixes this so 1351 mice should perfectly work now at least with the de-jitter option enabled.