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MIPSfpga / mipsfpga-plus

MIPSfpga+ allows loading programs via UART and has a switchable clock
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bringing bus to AMBA 3 AHB-Lite Spec and code refactoring #18

Closed zhelnio closed 7 years ago

zhelnio commented 7 years ago
  1. bus signals brought to correspond to AMBA 3 AHB-Lite Specification. Now for slave devices:
    • HREADY signal is input;
    • HREADYOUT signal was added;
  2. source files reorder:
    • mfp files moved to 'system_rtl' folder;
    • MIPSfpga CPU core code placed to 'core' folder;
    • all testbench files moved to 'testbebch' folder;
    • simulation scripts successfully updated and tested
  3. board qsf files update
    • qsf files were edited acording to new folder structure;
    • de10_lite tested on hardware;
    • de0_cv, de0_nano, de2_115, de10_nano checked with compilation in Quartus, Everything is Ok;
    • de0 checked with compilation in Quartus, works only when Area optimization is turned on and only with MIPSfpga 1.3;
    • de1 - not tested
  4. icarus verilog simulation script was updated and checked
  5. some code duplicate were deleted
  6. readme updated;
zhelnio commented 7 years ago

The integration with MIPSfpga 2.0 was also checked. Everything is fine.