Libero Scripted Designs Update towards Libero SoC v2023.1
MIV_RV32 in the designs has been updated from: v3.0.100 to v3.1.100. Some of the new features include: RISC-V F Extension and I-Cache.
Refactored TCL script library, updated for modularity, parameterization and input handling
New dynamic paths added, should allow for better performance on non-Windows based OS systems.
Removed glitches which may have been seen when adapting the designs for VHDL
Project folders for ES designs have been uniquified for clarity and traceability ying ES design folder names for clarity and traceability
Project folders for MIV_RV32, MIV_RV32IMAF and MIV_RV32IMA have been uniquified for clarity and traceability ying ES design folder names for clarity and traceability
Improved TCL output messaging with regards to the design building and design flow progression
An example software program has been added to LSRAM-based configurations. After programming the bitstream, software boots out of the box from the LSRAM.
The clocking circuitry in all of the designs (except MIV_RV32's CFG4) has been improved. A new 50MHz clock reference for the CCC has been added by replacing the RC Oscillator. Timing has been improved across the designs.
FlashPro_Express_Projects have been updated to reflect the latest design changes
Libero Scripted Designs Update towards Libero SoC v2023.1
Signed-off by: seb.slowikowski@microchip.com