VIA 6522 Timer countdown

[Rhialto]

Hi! How well is the VIA tested? I see this code fragment about timer 1:

// TIMER1
always @(posedge clk) begin
    if (reset) timer1 <= 16'hffff;
    else if (wr_strobe && addr == ADDR_TIMER1_HI) timer1 <= {data_in, timer1_latch_lo};
    else if (timer1 == 16'h0000 && ce && acr[6]) timer1 <= {timer1_latch_hi, timer1_latch_lo};
    else if (ce) timer1 <= timer1 - 1'b1;
end

If I see this correctly, the 3rd condition is about reloading the latch value into the timer, when the timer is $0000.

However, if the latch value is N, the timer counts N, N-1, N-2, ..., $0000, $FFFF and is only then reset back to N. T1 interrupts are N+2 cycles apart, and shifts of the shift register are twice that time apart.

I'm not well versed in reading verilog yet, so perhaps I'm reading this wrong, but at first glance the code seems wrong here. I am on the other hand well versed with the VICE version of the VIA.

Compare https://github.com/MiSTer-devel/Apple-II_MiSTer/blob/master/rtl/mockingboard/via6522.vhd#L454 where the intermediate signal timer_a_reload causes a cycle of delay after reaching $0000. The VIA in BeebFPGA has a similar signal (https://github.com/hoglet67/BeebFpga/blob/master/src/common/m6522.vhd) though as a whole it seems more complicated and it even seems to have a CLK which is separate from and some factor faster than the PHI2 clock. There is also a nice CRTC there which maybe can be used for more PET models.

[Rhialto]

https://github.com/skibo/Pet2001_Arty/blob/master/Pet2001_Arty.srcs/source_1/pet2001hw/via6522.v seems to be an updated version of what's in this core. The issue I'm indicating here seems to be fixed in that version.

It looks like Thomas Skibo made more improvements which are worthwhile to pull in here.

[Rhialto]

Another option is the VIA which is in the C64 core for the floppy support: https://github.com/MJoergen/C64_MiSTerMEGA65/blob/master/rtl/iec_drive/iecdrv_via6522.vhd

[sorgelig]

i've updated the VIA. Try this build: PET2001.zip

[Rhialto]

Thanks! I have a Mega-65, and I am considering to port this PET core to the Mega, using the MiSTer-to-Mega framework, https://github.com/sy2002/MiSTer2MEGA65 . I also hope to extend the PET, such as adding disk storage and more models. This is the first time I'm doing this so I'm hoping I'm not biting off more than I can chew :-)

[sorgelig]

I hope in return you will offer updates to MiSTer core as well

[Rhialto]

Of course!