Sorry if this is a completely n00b question but how can I go about figuring out the e2e latency of a design generated by nngen? In the generated RTL (verilog) I can see the main_fsm and in the timing reports generated by Vivado I can see critical path/delay and etc. but I am not sure how long each step of your FSM takes.
I think I can synthesize one layer at a time and then combine that with the schedule_table in some way but again my question is how to figure out the e2e latency of a layer?
Btw thank you very much for releasing this, I have been struggling for several months to come up with feasible RTL designs for NNs and this package is very informative!
EDIT: actually I guess the n00b answer to my n00b question is to simulate using verilator and multiply the number of cycles times the delay along the critical path.
Sorry if this is a completely n00b question but how can I go about figuring out the e2e latency of a design generated by
nngen? In the generated RTL (verilog) I can see themain_fsmand in the timing reports generated by Vivado I can see critical path/delay and etc. but I am not sure how long each step of your FSM takes.I think I can synthesize one layer at a time and then combine that with the
schedule_tablein some way but again my question is how to figure out the e2e latency of a layer?Btw thank you very much for releasing this, I have been struggling for several months to come up with feasible RTL designs for NNs and this package is very informative!
EDIT: actually I guess the n00b answer to my n00b question is to simulate using verilator and multiply the number of cycles times the delay along the critical path.