NYU-Processor-Design nyu-core issues

NYU-Processor-Design / nyu-core

The code and tests for the RISCV-32I compatible core for the NYU Processor Design VIP team.

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wip(<General Control Module>):

#174 cameronbed opened 1 month ago
1
tests: Fixed Con_ID tests not running and made many of the tests faster

#173 ShinyMiraidon closed 2 months ago
0
Test(memwb.cpp): fixed sign ext function

#172 ShinyMiraidon closed 2 months ago
0
Update CMakeLists.txt

#171 ShinyMiraidon closed 2 months ago
0
module(L1_Instruction_cache)

#170 xingzhi0420 closed 2 months ago
0
Fix reset line

#169 ShinyMiraidon closed 2 months ago
0
(Docs): Fix Hex Formatting in Module related Docs

#168 ShinyMiraidon opened 3 months ago
0
Create L1 Instruction Cache

#167 102934958086890 closed 3 months ago
1
Update 14_L1_Instruction_Cache.md

#166 102934958086890 closed 3 months ago
0
module(l1_data_cache): Added test and fixed issues with module

#165 ShinyMiraidon closed 2 months ago
1
docs(module outlines): Added memory related I/O to instruction cache related modules

#164 ShinyMiraidon closed 3 months ago
0
module(Branching_Control_Connection)

#163 xingzhi0420 closed 4 months ago
1
test(con_branch_cont.cpp)

#162 xingzhi0420 closed 4 months ago
0
test(branch_manager.cpp) Fixed errors in test

#161 ShinyMiraidon closed 4 months ago
0
Docs(Data Cache Connection Module Outline): Finished outline for the Data Cache Connection Module

#160 ShinyMiraidon closed 4 months ago
0
module(data_cache_manager): Added module and test

#159 ShinyMiraidon closed 4 months ago
0
Docs(Data_Cache_Manager_Outline.md): Outlined Data Cache Manager Module

#158 ShinyMiraidon closed 4 months ago
0
test(con_branch_cont)

#157 xingzhi0420 closed 4 months ago
0
Module(L1_Data_Cache): Updated Test Bench

#156 ShinyMiraidon closed 4 months ago
0
module(L1_Data_cache): Added data_mode input and functionality

#155 ShinyMiraidon closed 4 months ago
0
module(L1_Data_Cache.sv): Replaced L2 references

#154 ShinyMiraidon closed 4 months ago
0
docs(dev test and getting started): Updated dev and test doc and Created getting started core doc

#153 gil92723 closed 4 months ago
1
Tests(All): Test format update

#152 ShinyMiraidon closed 4 months ago
1
Task: Fix all the tests

#151 ShinyMiraidon closed 4 months ago
0
Revert "refactor: Formatting and syntax fixes"

#150 ShinyMiraidon closed 5 months ago
1
Revert 148 fix tests

#149 ShinyMiraidon closed 5 months ago
0
test(Alu): Fix alu test, demonstrate testing style

#148 nickelpro closed 5 months ago
2
refactor: Formatting and syntax fixes

#147 nickelpro closed 5 months ago
2
Con_Branch_Cont(test)

#146 xingzhi0420 closed 4 months ago
3
Created a getting started doc for core

#145 gil92723 closed 4 months ago
1
docs(00_Top_Level.md): Finished Top Level Connection Module Outline

#144 ShinyMiraidon closed 5 months ago
0
module(branch_manager): Fixed errors

#143 ShinyMiraidon closed 5 months ago
0
Document: Introduction and Team Guide

#142 ShinyMiraidon closed 3 months ago
0
connection_module(CmakeLists): compile test

#141 xingzhi0420 closed 5 months ago
0
add(Con_ID.sv, con_id.cpp): Added Implementation and Test for ID Connection Module

#140 ShinyMiraidon closed 5 months ago
2
update docs(10_L1_Data_Cache.md, 03_L1_Data_Cache.md), rtl(L1_Data_Ca…

#139 suriyasaiyan closed 4 months ago
4
docs(Con_Branch_cont): dev test not finish, maybe wrong

#138 xingzhi0420 closed 5 months ago
2
docs(L1_Instruction_Cache, Instruction_Cache_Manager): Updated input, output, registers

#137 thuvu17 closed 1 month ago
4
connection_module(Con_EX): Finished implementation and tests

#136 ShinyMiraidon closed 7 months ago
0
docs(04_ID_Connection_Module.md, 05_EX_Connection_Module.md, 07_Branching_Control_Connection_Module.md): Finished outlines for the ID, EX, and Branching Control Connection Modules

#135 ShinyMiraidon closed 7 months ago
0
Connection Module: Branching Control

#134 ShinyMiraidon opened 7 months ago
0
docs(03_IF_Connection_Module.md): Finished connection module outline

#133 ShinyMiraidon closed 7 months ago
0
docs(Added IO to cache outlines)

#132 ShinyMiraidon closed 7 months ago
0
move(interfaces): Moved interfaces to on hold

#131 ShinyMiraidon closed 7 months ago
0
Task: Confirm full ISA functionality

#130 ShinyMiraidon opened 7 months ago
0
Task: Connect Caches to AMBA for memory access

#129 ShinyMiraidon opened 7 months ago
0
Interfaces: Fixed syntax

#128 ShinyMiraidon closed 7 months ago
0
Revert "docs(10, 03_L1_Data_Cache.md): Updated Documentation"

#127 ShinyMiraidon closed 7 months ago
0
Interfaces: Fixed syntax

#126 ShinyMiraidon closed 7 months ago
0
docs(04_MEM_Connection_Module.md): Finished outline for MEM connection module

#125 ShinyMiraidon closed 7 months ago
0