Accessing UART3 on Hikey 960

[a2t2]

Hikey 960 has UART3 on the low speed header (https://www.96boards.org/documentation/consumer/hikey/hikey960/hardware-docs/hardware-user-manual.md.html#expansion-connectors). I am trying to read / write data on this UART3 from OPTEE.

I tried to use the existing pl011 driver. From the question, I find the physical address for UART3 is 0xffd74000.

When I use this address in the function io_pa_or_va() used in the pl011, I get the translated address value as 100, due to which the OPTEE crashes in the next line when it attempts to write using this address.

Can anyone help me resolve this issue ?

[jforissier]

Hi @a2t2,

Have you added register_phys_mem[_pgdir]()?

[a2t2]

Where should I add this line ? Its not present in the original pl011 driver. I am using the branch downloaded as shown in link.

[a2t2]

I also tried to test with calls to phys_to_virt(pbase, type) using various TEE memory types, and I always get a return value of zero.

[jforissier]

$ git grep register_phys_mem.*UART
core/arch/arm/plat-d02/main.c:register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE,
core/arch/arm/plat-hikey/main.c:register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
core/arch/arm/plat-hisilicon/main.c:register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
core/arch/arm/plat-imx/main.c:register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE,
core/arch/arm/plat-k3/main.c:register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE,
core/arch/arm/plat-ls/main.c:register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE,
core/arch/arm/plat-marvell/main.c:register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE,
core/arch/arm/plat-poplar/main.c:register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
core/arch/arm/plat-rcar/main.c:register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, SCIF_REG_SIZE);
core/arch/arm/plat-sam/main.c:register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE,
core/arch/arm/plat-stm/main.c:register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART_CONSOLE_BASE, STIH_ASC_REG_SIZE);
core/arch/arm/plat-stm32mp1/main.c:register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART4_BASE, SMALL_PAGE_SIZE);
core/arch/arm/plat-stm32mp1/main.c:register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART5_BASE, SMALL_PAGE_SIZE);
core/arch/arm/plat-stm32mp1/main.c:register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART7_BASE, SMALL_PAGE_SIZE);
core/arch/arm/plat-stm32mp1/main.c:register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART8_BASE, SMALL_PAGE_SIZE);
core/arch/arm/plat-synquacer/main.c:register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE,
core/arch/arm/plat-ti/main.c:register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE,
core/arch/arm/plat-vexpress/main.c:register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
core/arch/arm/plat-zynq7k/main.c:register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE,

[a2t2]

I'm guessing you want me to add it to core/arch/arm/plat-hikey/main.c ? register_phys_mem() is taking 3 arguments. Should I add: register_phys_mem(MEM_AREA_IO_SEC, 0xffd74000 , PL011_REG_SIZE) ?

[a2t2]

I added register_phys_mem(MEM_AREA_IO_SEC, 0xffd74000 , PL011_REG_SIZE) in core/arch/arm/plat-hikey/main.c and used phys_to_virt() with mem type IO_SEC. I got the virtual address 0x3cd74000. The pl011_init() function gets stuck at pl011_flush() call (while loop with base = 0x3cd74000).

Error messages after it gets stuck for 2 minutes:

I changed the memory type to IO_NSEC in core/arch/arm/plat-hikey/main.c and got the virtual address 0x3ad74000. The pl011_init() function still gets stuck when trying pl011_flush(). Message displayed after 20 seconds:

If I comment out the pl011_flush() call, and then try to do use pl011_putc(), it gets stuck at line.

Any suggestions ?

[jforissier]

Try IO_NSEC maybe?

[a2t2]

I already tried IO_NSEC (the second screenshot).

Is UART 3 enabled when a AOSP + OPTEE branch is compiled ? I tried a test where I changed the platform config to make OPTEE console log go to UART3. The Hikey 960 board never booted completely (I didn't even get normal world console prompt). This tells me there is some kind of configuration missing for UART3 in the branch, but I'm not sure what to change to enable use of UART3.

[jforissier]

I already tried IO_NSEC (the second screenshot).

Sorry I missed that :-/ replied on my smartphone and a bit too quickly...

Is UART 3 enabled when a AOSP + OPTEE branch is compiled ?

Well, I don't know. Perhaps some specific clock has to be enabled. I have never used UART 3 on my HiKey 960.

[a2t2]

Is it possible you could tell me how exactly to enable the UART3 clock ? There is related comment at link, but just looking at that clock related file, I don't know what to change to enable UART3. Thank you.

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[warraagal]

Is it possible you could tell me how exactly to enable the UART3 clock ? There is related comment at link, but just looking at that clock related file, I don't know what to change to enable UART3. Thank you.

@a2t2 did you find an answer to your question ?

[a2t2]

@warraagal No I didn't.