OpenXiangShan / XiangShan

Open-source high-performance RISC-V processor
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In VCS simulation, multi-core simulation of some harts ended prematurely due to incorrect execution of SEQZ instruction #3084

Open meiqin0 opened 3 months ago

meiqin0 commented 3 months ago

Before start

Describe the bug

我在仿真多hart的时候,发现四个hart有部分hart没有等到同步点而是提前结束了,然后找了一下问题,发现好像是伪指令seqz没有正确。

[TRANSLATION]

During the simulation of multiple harts, I noticed that some of the four harts ended prematurely without waiting for the synchronization point. Upon further investigation, it seems that the pseudo-instruction SEQZ was not executed correctly.

cb94fe3f83541b1dd4a3c27afa0118cd

后面80003a8a这条分支指令的src0/1都是0, a4寄存器没有取反,应该是80003a66指令没有执行:

[TRANSLATION]

The source registers src0/1 for the branch instruction at 80003a8a are both zero, and register a4 has not been inverted, which suggests that the instruction at 80003a66 was not executed:

efa400ce072deb1456f9c95dccc4eaf8

测试用例基于am->amtest, 问题发生点位于mpe.c的_barrier函数:

[TRANSLATION]

The test case is based on am->amtest, and the point of issue is located in the _barrier function of mpe.c:

e8e52efecc8dc2701820e4c5fbd59b85

Expected behavior

应该等到4个hart都到达同步点后再打印结果(正确):

[TRANSLATION]

The results should be printed only after all four harts have reached the synchronization point (correct):

image 而不是部分hart提前结束(此错误): [TRANSLATION] Instead of some harts ending prematurely (this is the error): image

To Reproduce

elf,bin,dasm amtest-riscv64-xs-dual.zip

Environment

Additional context

注:需要使用vcs仿真,verilator发现不了这个错误。

[TRANSLATION]

Note: VCS simulation is required, as Verilator cannot detect this error.

Tang-Haojin commented 3 months ago

感谢您的反馈,多核的测试尚不充分,我们后续会进一步调查这一问题。

[TRANSLATION]

Thank you for your feedback. The multi-core testing is still insufficient, and we will further investigate this issue in the follow-up.