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Origen-SDK / origen_sim

Plugin to enable Origen patterns to be run in a dynamic Verilog simulation
MIT License
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Fix hard coded pin paths at different locations making use of the testbench_top variable #59

Open mathieuperret01 opened 1 year ago

mathieuperret01 commented 1 year ago

Hi All,

Needed to add the options[:testbench_top] called also for forced signals in the template/probe.tcl.erb. I also modified the origen_sim/origen_tester/api.rb, which also has a hard coded 'origen.dut' in the sim_capture function.

So the hard coded path: origen.dut or origen.debug is now removed from the template/probe.tcl I noticed it is also present at other locations: like in template/empty.svcf (and others), which makes that default setup signals cannot be found, in case a different testbench_top is used (i.o. 'origen') => problem is that this emty.svcf (and others) is not an .erb file, and is not compiled in origen_sim => it would be nice to have that implemented, but I am not sure how.

ginty commented 1 year ago

I think for the ones that are not templates today, it's just a matter of renaming them, e.g. empty.svcf => empty.svcf.erb (to indicate that they contain dynamic content) and then adding whatever dynamic markup you need.

Would indeed be good to update them all in this PR if you can.

mathieuperret01 commented 1 year ago

Hi Stephen, Yes, I did try that. (naively ? :)) But the empty.svcf.erb is not compiled, and saved as is, in the waves. So I guess, a compile must be implemented in origen_sim for this specific files, is we change them to .erb

mathieuperret01 commented 1 year ago

Hi All, Can we merge this PR ? I am also wondering: what's next: new tag ? new gem ? Thanks.