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PaxInstruments / labwiz-board

A development board based on the STM32 series processors specifically targeting the STM32F103RxT series.
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Put USART3 on modules #133

Open charlespax opened 7 years ago

charlespax commented 7 years ago

Right now all four modules share USART2 while USART3 is dedicated to the wifi modules. Maybe we should have modules 1 and 2 share USART while modules 3 and 4 share USART3. screen shot 2017-01-24 at 17 49 55

electrokean commented 7 years ago

If you're going to share the USART between module slots, can I suggest using AND gates on the receive pins to avoid electrical contention. Something like the 74LVC1G08 or 74LVC2G08. Else, I'd suggest only connecting two module slots.

charlespax commented 7 years ago

Good call. Do you mean AND gate or OR gate?

I think we would want a four input OR gate (one for each module TX) with the output going into STM32 RX. The STM32 TX and each module RX would be directly connected.

The SPI MISO lines maybe should also be on OR gates unless SPI already handles this. TSTM32 host would be in control of each SPI chip select pin, so we probably don't need that. I2C should be fine since it's made to handle the electrical contention issue.

All modules listen to the sam TX signal form the STM32. If there were a problem for a module, it could be designed to use one of the GPIO lines. On the module, connect a GPIO pin and STM32 TX to a two input AND gate. The output is connected to the RX pin of the receiving chip.

charlespax commented 7 years ago

Maybe just kill the idea of serial on all modules. We can take the STM32 RX and TX pins and use them as GPIO. If we route them both to either modules 2 or 4, then that module can have an extra capability

electrokean commented 7 years ago

I did mean AND gate. The UART signals idle in a high state, so are active low. An AND gate can be used to combine the negative logic. I was thinking you'd use two of the tiny 2 input AND gates, to combine the RX signals coming from each pair of modules into USART2 and USART3 repectively.

The idea would be that the modules would act in a kind of multi-drop bus architechture. You could use a GPIO or some address jumpers on each module to make them unique.

If you're going to keep the ESP8266, then I guess you only have USART2 available? In that case you'd need a 4-input AND gate. No such thing in the TinyLogic families, but you could use two 3-input ANDs e.g. 74LVC1G11 or NC7SZ11. The SOT363/SC-70-6/SC-88 packages don't take up much space.

Regarding SPI, the DO lines on well behaved SPI slaves should tri-state. Check the link I posted in #125 re SPI best practices. If an SPI slave device on a module is not well behaved, the module should implement a separate tri-state buffer.