Preethiaralikatti VSDIAT issues - Githubissues

Preethiaralikatti / VSDIAT

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Day 5 -Final Steps For RTL2GDS Using TritonRoute and OpenSTA Routing and Design Check [DRC]

#5 Preethiaralikatti opened 7 months ago
14
Day 4 -Pre-Layout Timing Analysis and Importance of Good Clock Tree

#4 Preethiaralikatti opened 7 months ago
12
Day 3 -Design Library Cell Using Magic Layout and NGSPICE characterisation

#3 Preethiaralikatti opened 7 months ago
18
Day 2 -Good vs Bad Floorplan and Introduction to Library Cells

#2 Preethiaralikatti opened 7 months ago
15
Day 1 -Inception of OpenSource EDA, OpenLANE and SKY130 PDK

#1 Preethiaralikatti opened 7 months ago
11