Day 2 -Good vs Bad Floorplan and Introduction to Library Cells

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Chip Floor Planning Considerations

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Utilisation Factor and Aspect Ratio

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Concept of Pre-Placed Cells

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De-Coupling Capacitors

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Power Planning

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Pin Placement and Logical Cell Placement Blockage

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Steps to run floorplan using OPENLane

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Optimise Placement Using Estimated Wire-Length and Capacitance

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Cell Design and Characterisation Flows

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Inputs for Cell Design Flow

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General Timing Characterisation Parameters

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Timing Threshhold Definitions

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Propogation Delay and Transition Time

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Layout Design