PyHDI / Pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL
Apache License 2.0
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Task call parsing failure #66

Open VibhorDodeja opened 4 years ago

VibhorDodeja commented 4 years ago

Unable to parse task calls using pyverilog.

Failure signature: (fail.log)

Syntax error
Traceback (most recent call last):
  File "task_parse.py", line 5, in <module>
    ast, direct = parse(vfiles, [], [])
  File "/home/vdodeja2/.local/lib/python3.7/site-packages/pyverilog/vparser/parser.py", line 2322, in parse
    ast = codeparser.parse()
  File "/home/vdodeja2/.local/lib/python3.7/site-packages/pyverilog/vparser/parser.py", line 2300, in parse
    ast = self.parser.parse(text, debug=debug)
  File "/home/vdodeja2/.local/lib/python3.7/site-packages/pyverilog/vparser/parser.py", line 77, in parse
    return self.parser.parse(text, lexer=self.lexer, debug=debug)
  File "/home/vdodeja2/.local/lib/python3.7/site-packages/pyverilog/vparser/ply/yacc.py", line 265, in parse
    return self.parseopt_notrack(input,lexer,debug,tracking,tokenfunc)
  File "/home/vdodeja2/.local/lib/python3.7/site-packages/pyverilog/vparser/ply/yacc.py", line 1047, in parseopt_notrack
    tok = self.errorfunc(errtoken)
  File "/home/vdodeja2/.local/lib/python3.7/site-packages/pyverilog/vparser/parser.py", line 2272, in p_error
    self._coord(p.lineno))
  File "/home/vdodeja2/.local/lib/python3.7/site-packages/pyverilog/vparser/plyparser.py", line 55, in _parse_error
    raise ParseError("%s: %s" % (coord, msg))
pyverilog.vparser.plyparser.ParseError: :25: before: (

Verilog code: (task_example.v)

module task_example ();

  reg [7:0] r_Mux_Addr_Data = 0;
  reg       r_Addr_Valid = 1'b0;
  reg       r_Data_Valid = 1'b0;

  task do_write;
    input [7:0] i_addr, i_data; 
    begin
      // demonstrates driving external Global Reg
      r_Addr_Valid    = 1'b1;
      r_Mux_Addr_Data = i_addr;
      #10;
      r_Addr_Valid    = 1'b0;
      r_Data_Valid    = 1'b1;
      r_Mux_Addr_Data = i_data;
      #10;
      r_Data_Valid = 1'b0;
      #10;
    end
  endtask

  always @(*)
    begin
      #10 do_write(8'h01, 8'hBC);
      //do_write(8'h01, 8'hBC);
      //do_write(8'h02, 8'hCD);
    end

endmodule

Python script to parse the verilog (task_parse.py)

from pyverilog.vparser.parser import parse

vfiles = ["./task_example.v"]

ast, direct = parse(vfiles, [], [])

ast.show()

Environment: OS: Ubuntu 18.04.5 LTS Python version: 3.7 PyVerilog version: 1.2.1

Attaching above files: task_failure.zip

shtaxxx commented 4 years ago

Task-call statement support is under development with SystemVerilog support on feature_systemverilog branch. Stay tuned!