[AMDGPU][MC][GFX9] Disassembler failed to decode SMEM with IMM=0 and OFFSET>127

[Quuxplusone]

Bugzilla Link	PR49819
Status	RESOLVED FIXED
Importance	P enhancement
Reported by	Dmitry Preobrazhensky (d-pre@mail.ru)
Reported on	2021-04-02 06:28:37 -0700
Last modified on	2021-04-13 05:42:24 -0700
Version	trunk
Hardware	PC Windows NT
CC	llvm-bugs@lists.llvm.org, stanislav.mekhanoshin@amd.com
Fixed by commit(s)	rG3eadcb8
Attachments
Blocks
Blocked by
See also

Debug build of disassembler triggers an assert when trying to decode the
following GFX9 code:

    0xc28948ff, 0x48b84d8b

The code is actually an illegal variant of s_atomic_add_x2:

SOFFSET      OFFSET                        OP     IMM GLC SOE SDATA   SBASE
|            |                             |        | |   |   |       |
0100100.0101.110000100110110001011  110000.10100010.0.1.0.1.0.0100011.111111
|                                          |                  |       |
36                                         162                35      EXEC=126

The code is invalid for several reasons including:
  - unaligned SDATA
  - SBASE=EXEC
  - IMM=0 but OFFSET is not a valid SGPR

The last issue caused disassembler to assert.

[Quuxplusone]

Actually the code has SOE=1 so OFFSET should be ignored and SOFFSET used
instead. sp3 decodes this code as the following instruction:

    s_atomic_add_x2  s[35:36], exec, s36 glc

But llvm does not currently supports SOE. Anyway it should not fail trying to
decode a large OFFSET value as an SGPR.