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RTimothyEdwards / capiche

Parasitic capacitance analysis of foundry metal stackups
GNU General Public License v2.0
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Metal stackup file for sg13g2 #5

Open mole99 opened 2 months ago

mole99 commented 2 months ago

This is the work in progress sg13g2 metal stackup file.

There are still some bits I'm unsure about, especially in the lower and upper layers.

Note: The height calculations are written out in full, to make it easer to find any errors.

rfscholz commented 2 months ago

Hi oxide thickness for MOS devices are only few nanometer. Can you explain why you need it? It is not part of process spec up to now. I need to check if we are allowed to disclose it.

For TM2 the first one is also oxide with 4.1 the second one is silicon nitride with 6.6. Sidewalls are not exactly measured. So your estimation should be OK. For which purpose you need such exact numbers here?

mole99 commented 2 months ago

Hi Rene, thanks for your reply!

We would need the oxide thickness to calculate the top height of diff/hvdiff, as I understand it. But maybe @RTimothyEdwards can clarify that a bit.

Yes, an estimation should suffice, we don't need exact numbers. But I thought it would still be great to have the proper values if they are available :)

RTimothyEdwards commented 2 months ago

@rfscholz : I have been using the IHP open PDK definition to determine which devices should be implemented. I am referencing IHP-Open-PDK/ihp-sg13g2/libs.doc/doc/SG13G2_os_process_spec.pdf. Page 9 described the HV nMOS and pMOS devices, and page 10 describes the HV native nMOS device.

For the sidewall dielectric thickness: An estimated distance is fine for the purpose of running the parasitic calculations, as there will be a negligible impact on the parasitic capacitance. I just didn't want to throw in a made-up number if an exact one was available. Having worked on open PDKs, I'm well aware of how an estimated value, once pushed to an open PDK repository, will be accepted as verified fact by unwitting users. : ) We will proceed with the estimated value and a comment to clarify.

RTimothyEdwards commented 2 months ago

@rfscholz : More specifically, the SG13G2_os_process_spec.pdf file page 17 lists the thin oxide thickness as 2.65nm nominal and the thick oxide thickness as 7.5nm nominal. This information is already in the public domain.

mole99 commented 2 months ago

Sorry for the wrong alert then, it seems I overlooked the oxide thicknesses!

rfscholz commented 2 months ago

OK perfect I also overlooked it 🙂. Do you want to use it for parasitic extraction? Usually active devices like CMOS are excluded. For Poly resistors the detailed stack is available on page 6.

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Sorry for the wrong alert then, it seems I overlooked the oxide thicknesses!

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mole99 commented 2 months ago

Whoops, it seems part of the email got appended ^^ You can edit your comment if you want.

Yes, it is used for parasitic extraction, @RTimothyEdwards could explain for what exactly. Thanks, I've already made good use of the stackup on page 6 😃

RTimothyEdwards commented 2 months ago

@rfscholz : It is only used to calculate parasitic coupling from metal layers down to diffusion, e.g., source and drain diffusion. Diffusion under a gate is always assumed to be part of the device model.