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RedPitaya
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RedPitaya-FPGA
Repository for FPGA projects
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Release 2024.2
#11
b-swat
closed
4 months ago
0
Release 2024.1
#10
b-swat
closed
6 months ago
0
Fixing some problems with triggering on 250 and data valid pulse alig…
#9
b-swat
closed
9 months ago
0
update to latest Vivado 2023.1
#8
marcomeixner
closed
4 months ago
3
Release 2023.2
#7
b-swat
closed
12 months ago
0
STEMlab 125-14 4-Input IDELAY for ADC data lines
#6
vborchsh
closed
1 year ago
1
Lesson fix
#5
Lightsaver7
closed
1 year ago
0
Lessons fix
#4
Lightsaver7
closed
1 year ago
1
Release 2023.1
#3
b-swat
closed
1 year ago
0
Unresolved merge conflict
#2
tobiasriesen
closed
1 year ago
2
Arbitrary Signal Generator: Ch A buffer current read pointer on fpga_0.94 always read as 0
#1
VacumMastah
closed
1 year ago
1