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RoaLogic / RV12

RISC-V CPU Core
Other
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Design elaboration failed in Xilinx Vivado #25

Closed kshitij-r closed 2 years ago

kshitij-r commented 3 years ago

I tried elaborating the design in Xilinx Vivado and included all the necessary packages(Memory and AHB3Lite). But the design does not elaborate in Vivado and gives this error : [Synth 8-1031] EXCEPTION_SIZE is not declared ["/home/raj/Documents/Vivado Projects/RV12/RV12.srcs/sources_1/imports/Desktop/RV12/rtl/verilog/core/ex/riscv_bu.sv":61]

The package is hows as grey in the project explorer which means that the file containing the package is not being used.

rherveille commented 2 years ago

This should be fixed in dev branch