Currently, the AMDS driver (as implemented in firmware v1.3) has hard-coded timeout values. These timeouts are necessary in the case that the timing manager triggers the AMDS to sample (via the SYNC_ADC interrupt), but the AMDS is unable to return data due to an unplugged/faulty/etc data line connection.
If the driver did not have the ability to time out, it would wait forever to receive the data from the AMDS, and never assert that its data acquisition is done, thus freezing the timing manager. Not ideal.
Currently, the trigger-to-first-data-packet timeout is hardcoded to ~10us in amdc_amds_v1_0_S00_AXI.v:
Currently, the AMDS driver (as implemented in firmware
v1.3) has hard-coded timeout values. These timeouts are necessary in the case that the timing manager triggers the AMDS to sample (via the SYNC_ADC interrupt), but the AMDS is unable to return data due to an unplugged/faulty/etc data line connection.If the driver did not have the ability to time out, it would wait forever to receive the data from the AMDS, and never assert that its data acquisition is done, thus freezing the timing manager. Not ideal.
Currently, the trigger-to-first-data-packet timeout is hardcoded to ~10us in
amdc_amds_v1_0_S00_AXI.v:https://github.com/Severson-Group/AMDC-Firmware/blob/0d27cc0f0cdc9f627493bc45ff0d6b0998f531a7/ip_repo/amdc_amds_1.0/hdl/amdc_amds_v1_0_S00_AXI.v#L592-L607
and the timeout between individual UART bytes is hardcoded to 2.5us in
uart_rx.vhttps://github.com/Severson-Group/AMDC-Firmware/blob/0d27cc0f0cdc9f627493bc45ff0d6b0998f531a7/ip_repo/amdc_amds_1.0/src/uart_rx.v#L171-L191
These hardcoded timeout values should be replaced with a way to configure a value in a slave register from the C code.
Relevant Development History:
393
394