SpinalHDL NaxRiscv issues

SpinalHDL / NaxRiscv

MIT License

269 stars 40 forks source link

issues

Newest

Newest Most commented Recently updated Oldest Least commented Least recently updated

Improvements: Updating Spike and RVLS Submodules

#126 Bill94l opened 1 week ago
2
Update simulator for compatibility with the updated spike version

#125 Bill94l opened 1 month ago
0
About performance evaluation

#124 yyyjjp closed 1 month ago
1
Is there any implementation of FENCE instructions?

#123 zyn810039594 closed 1 month ago
2
How to run a bare metal program with mulitple cpus

#122 phillippZZ closed 3 months ago
0
Performance counter CSR registers that are not implemented are seen as implemented

#121 Bill94l closed 3 months ago
2
Handle Illegal RVC Instructions and Mask Upper Bits in mtval for RVC Traps

#120 Bill94l closed 3 months ago
1
about the gen.scala and ifetch

#119 duanjiulon opened 4 months ago
18
Need help with the infrastructure regarding interconnection

#118 phillippZZ closed 4 months ago
6
Updating the memory mapping for SocDemo

#117 Bill94l closed 4 months ago
4
Nax not trap on store fault

#116 atkarim opened 4 months ago
5
Fix the check of the register Rd is not equal to zero for c.lwsp instruction and Update IO rang addresses

#115 Bill94l closed 1 month ago
4
The check of the register Rd/Rs is not equal to zero is missing for some compressed instructions

#114 Bill94l closed 3 months ago
2
How to integrate my own IP

#113 phillippZZ closed 4 months ago
3
WFI instruction

#112 Bill94l closed 4 months ago
11
storeFresh unused : trap-store_access_fault

#111 Bill94l closed 1 month ago
5
A trap is triggered when the pmpcfg register is read by csrr

#110 Bill94l opened 4 months ago
8
Question about the sizes of cache L2 & L1

#109 phillippZZ closed 3 months ago
7
Accessing addr 0x0000001e doesn't throw access fault exception

#108 zhangkanqi closed 5 months ago
3
Does NaxRiscv update mtval after trap illegal_inst?

#107 zhangkanqi opened 5 months ago
2
[Bug Report] Executing `sfence.vma` under U-mode doesn't throw illegal inst exception

#106 zhangkanqi closed 5 months ago
0
Wrong value of `sie` after trapping store_access_fault

#105 zhangkanqi closed 5 months ago
1
Read data incorrectly when executing `c.lwsp` instruction

#104 zhangkanqi closed 5 months ago
9
Does NaxRicv support S-mode?

#103 zhangkanqi closed 5 months ago
12
How to customize hardware architecture

#102 phillippZZ closed 5 months ago
15
NaxRiscv sets sepc[0]=1 which is against the riscv privileged spec

#101 zhangkanqi closed 5 months ago
3
NaxRiscv gets the wrong value when reading from `scause`

#100 zhangkanqi closed 6 months ago
4
An exception arose when reading instructions from the ELF file

#99 zhangkanqi closed 5 months ago
15
Problems about debug and Halt the Nax

#98 xie-1399 closed 6 months ago
8
Non blocking cache

#97 SoCScholar closed 5 months ago
6
about litex and dhrystone

#96 duanjiulon opened 6 months ago
41
Error in implementation of SRAW and SRAIW instructions

#95 Nanotrust opened 7 months ago
3
L1 cache communication with CPU core

#94 SoCScholar closed 5 months ago
0
Memfilter and interface/Tilelink channel communicating with L2 cache and Memfilter

#93 SoCScholar closed 5 months ago
0
Changing Naxriscv instructions - command

#92 mdmriscv opened 7 months ago
1
L1/L2 cache and integration with CPU pipeline

#91 SoCScholar opened 7 months ago
2
Read a sram that is changed by other host

#90 zyn810039594 opened 7 months ago
1
Some guidance on better timing

#89 tristanitschner opened 7 months ago
3
The mmu_sv39.elf fail with SocSim

#88 Bill94l closed 5 months ago
18
cache_throttling && dirty evicts counting.

#87 SoCScholar closed 4 months ago
10
LINUX on Litex_NaxRISCV ( Linux-capable, RISC-V-based SoC )

#86 SoCScholar closed 8 months ago
17
Fix wrong mask for 64 bits IO access

#85 Bill94l closed 8 months ago
1
Wrong mask for 64 bits IO access in NaxRiscvProbe

#84 Bill94l closed 8 months ago
1
riscv tests with virtual memory enabled fail

#83 Bill94l opened 9 months ago
3
Hi,can you privide an example?

#82 duanjiulon closed 7 months ago
56
how to run a nax_core with a AXI4 interface

#81 duanjiulon opened 9 months ago
13
README.md: touch-ups by a native English speaker

#80 ldoolitt closed 9 months ago
2
Default branch direction prediction should be TAKEN (currently NOT TAKEN)

#79 ronan-lashermes opened 9 months ago
1
[BUG] CSR write verification error in the Verilator wrapper

#78 Bill94l opened 10 months ago
5
ext/NaxSoftware/init.sh not up-to-date

#77 Bill94l closed 10 months ago
1