Wrong mask for 64 bits IO access in NaxRiscvProbe

Hi Charles, The current mask value is zero for 64-bit access. https://github.com/SpinalHDL/NaxRiscv/blob/8f0bd88d2bad93d4c6e5fcabae83391453888c13/src/main/scala/naxriscv/platform/NaxriscvProbe.scala#L266

When booting Linux "rv64imafdcsu" with SocSim & RVLS, I got the following error:

[info] *** INTEGER WRITE MISSMATCH DUT=216309d REF=0 ***
[info] commit error
[info] - std::exception

For debugging, I saw the spike.log , tracer.log and the output waves :

**SPIKE.LOG**
core   0: 0x0000000080008f22 (0x00006108) c.ld    a0, 0(a0)
core   0: 3 0x0000000080008f22 (0x6108) x10 0x0000000000000000 mem 0x000000001001bff8

**TRACER.LOG**
rv io 0 0 000000001001bff8 0000000000000000 ff 8 0
rv rf w 0 0 32 000000000216309d
rv commit 0 0000000080008f22

linux_boot_wave

In the output waves, we can see that the data at the address 0x1001bff8 is equal to 0x216309d, as shown in the following line from the tracer.log file

rv rf w 0 0 32 000000000216309d

In the spike.log instead of having this value 216309d. I have a data value which is equal to zero, this value is sent to RVLS via IOAccess as shown in the following line from the Tracer.log (because the value of the mask is zero)

rv io 0 0 000000001001bff8 0000000000000000 ff 8 0

Here is the modification that I made to the mask to have a mask that is equal to 0xFFFFFFFF for 64-bit access

     val mask = (BigInt(1) << ioAccess.size*8)-1
     ioAccess.data = (ioBus.rsp.data.toLong >> offset*8) & mask.toLong

Thank you !

SpinalHDL / NaxRiscv

Wrong mask for 64 bits IO access in NaxRiscvProbe #84