If I understand correctly, I've managed to derive a diagram from the provided code. I'm curious about how Memfilter communicates with L2 cache, specifically, the interfaces or channels involved, excluding MESI coherence. Could you please elaborate on the communication (interfaces or channels involved ) between Memfilter and L2 cache?
As I can see just below code, What are the channels inside memFilter.down to interface with A,C,D of L2 cache ?
cache.up << memFilter.down
cache.up.setUpConnection(a = StreamPipe.FULL, c = StreamPipe.FULL, d = StreamPipe.FULL)
How does channel A,C,D of L2 cache (UP) communicate with Memfilter, L1 cache?
Does channel A,D of L2 cache (DOWN) communicate with Main Memory controller (DRAM)?
Note: MBRU: is our memory bandwidth regulation controller.
https://github.com/SpinalHDL/NaxRiscv/blob/throttle_l2/src/main/scala/naxriscv/platform/litex/NaxSoc.scala#L76
Dear charles,
If I understand correctly, I've managed to derive a diagram from the provided code. I'm curious about how Memfilter communicates with L2 cache, specifically, the interfaces or channels involved, excluding MESI coherence. Could you please elaborate on the communication (interfaces or channels involved ) between Memfilter and L2 cache?
As I can see just below code, What are the channels inside memFilter.down to interface with A,C,D of L2 cache ?
How does channel A,C,D of L2 cache (UP) communicate with Memfilter, L1 cache?
Does channel A,D of L2 cache (DOWN) communicate with Main Memory controller (DRAM)?
Note: MBRU: is our memory bandwidth regulation controller.