ThalesGroup / cva6-softcore-contest

National RISC-V student contest CV32A6
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Bump verif/core-v-verif from `6779193` to `34d39b9` #32

Closed dependabot[bot] closed 6 months ago

dependabot[bot] commented 6 months ago

Bumps verif/core-v-verif from 6779193 to 34d39b9.

Commits
  • 34d39b9 Merge pull request #2415 from ThalesSiliconSecurity/fix/spike-param-handling
  • 3a25166 [Spike params] Add patch matching "Fix parameter handling: parsing, he..."
  • deb7545 [Spike params] Fix parameter handling: parsing, help, assignment order.
  • d4e32fc Merge pull request #2413 from MarioOpenHWGroup/fix/tandem-requirements-for-vcs
  • fc7ba9e Use IMPERAS as default ISS
  • f0a1ec9 Add VCS support for riscv-isa-sim tandem
  • f7bda8e Merge pull request #2409 from ludovicpion/master
  • 8b07974 remove artificial layer of heirarchy (bp_gen/bp_gen). It was a mistake
  • ba443fb remove artificial layer of heirarchy (bp_gen/bp_gen). It was a mistake
  • 31bcffe Changes to reply to issue #2403, #2407 and #2408
  • Additional commits viewable in compare view


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dependabot[bot] commented 6 months ago

The following labels could not be found: Component:Verif.

dependabot[bot] commented 6 months ago

Superseded by #33.