Closed akhilesh911 closed 2 weeks ago
The reproducible isn't working for some reason, looking into it. Meanwhile, can you upload your source files and config?
`suppress_faults
is a non-standard Verilog compiler directive, and will likely never be supported by our synthesis tool, Yosys.
You more likely than not have to just remove it from your design.
The source of the issue is including gf180mcu_fd_io.v
in the design input verilog sources files. By uploading the source files, I wanted to know whether this was absolutely needed and offer a workaround.
Staled out.
Description
Hello, While running synthesis on my design, there is an error in synthesis stage. ERROR: Unimplemented compiler directive or undefined macro `suppress_faults. The reproducible package is attached. Kindly guide.
Expected Behavior
Synthesis should be completed.
Environment report
Reproduction material
issue_reproducible.zip
Relevant log output