vhdl_testbench - Githubissues

TheSystemDevelopmentKit / rtl

Package for rtl (i.e. Verilog and VHDL ) simulation control

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vhdl_testbench #51

Closed mkosunen closed 1 year ago

mkosunen commented 1 year ago

This PR is for development of VHDL testbench to eventually support VHDL-only simulators.

mkosunen commented 1 year ago

Relates

[x] #53
[x] #54
[x] #55
[x] #56
[x] #57
[x] #58
[x] #59
[x] #60
[x] #61
[x] #62
[x] #64
[x] #66
[x] #67

mkosunen commented 1 year ago

Ping @Roenski , in case you are interested. I will work on this over coming weeks, but we can negotiate about some credits if you are willing to help. The workload is about the same as for verilator C - testbenches would be (which is next on the list :) ).

mkosunen commented 1 year ago

This has been tested with register_tempate and inverter.