when there is a transfer being done, the read and write packets needs to be smaller, because the internal memory to receive and send them packets are smaller. I believe that in bigger machine the Rx/Tx buffer is 8K, but in the F256x line it is only 2K... So some changes would required to support that.
For F256K and F256Jr modes, from Stefany:
when there is a transfer being done, the read and write packets needs to be smaller, because the internal memory to receive and send them packets are smaller. I believe that in bigger machine the Rx/Tx buffer is 8K, but in the F256x line it is only 2K... So some changes would required to support that.