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UA-RCL / CEDR

https://ua-rcl.github.io/projects/cedr/
MIT License
6 stars 1 forks source link

About the RISC-V Integrated framework #4

Closed ariusewy closed 1 week ago

ariusewy commented 1 month ago

Hi,

I noticed your extended CEDR on RISC-V Heterogeneous SoC Design. I wonder if the RISC-V integrated CEDR source code along with the FPGA image is available? I hope to conduct some DSE experiments based on this.

Thank you very much!

umutsuluhan commented 1 month ago

Hi, we are working on a release right now and hopefully we will make it public soon. Once we are done with it, I will ping you here.

umutsuluhan commented 2 weeks ago

Hi @ariusewy,

We have released the source code regarding RISC-V!

CEDR: https://github.com/UA-RCL/CEDR/tree/hcw-2024 FPGA and Linux Image: https://github.com/UA-RCL/Hardware-Images/tree/riscv-1boom-2big-3little-2fft

You can find the installation instructions in the respective README files in each repository. Please let me know if you have any issues and questions.

ariusewy commented 2 weeks ago

Thank you for your release, I'll have a try!