VHDL-LS / rust_hdl

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[Enhancement] Add more symbol kinds #161

Open pidgeon777 opened 1 year ago

pidgeon777 commented 1 year ago

With vhdl-linter, this is possible:

FSM cases as symbol scopes:

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Check of conditions in if-generate statements as symbol scopes:

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It would be great to also add those kinds of symbols to the currently available in rust_hdl.

Eventually, those could be enabled/disabled thanks to an LSP server configuration.

kraigher commented 1 year ago

Basically you can define levels of functionality what a language server should do. The core of a server is to handle the language specification. The specification is not optional and is shared by everyone.

On top of this there are things like coding styles and design rules. Those are not universal and team specific. The VHDL standard does not talk about state machines as far as I am aware, that is more of a design rule.

I am sure that adding configurable coding styles and design rules is valuable. Especially if there can be convergence towards a standard coding style in the community. It is just that at this stage of the project I see so many core features I would much rather work on.

My initial aim for this project was to build a good core VHDL language library that others could contribute this kind of rules and configuration on top of. I am still hoping someone will rise to the challenge. At this point in time I am not interested in doing this work myself and increasing the scope of my own work contribution. I might if it was my job and it was a commercial product but it is not.

There are plenty of project who provides linters based on slow and incomplete Python-implementations of VHDL. My hope is that those people would instead build upon my work.