Error in syntax highlighting when a block does not have anything in its header

[LukasVik]

This is as expected:

Removing the content of the header, I would not expect the highlighting to change:

Problem is present in released version as well as in https://github.com/VHDL-LS/rust_hdl_vscode/pull/66 commit 6e85242: Replacing old grammar..

Test file content:

library ieee;
use ieee.math_real.all;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;

entity syntax_highlight_test2 is
  generic (
    build_id : natural
  );
  port (
    led : out std_ulogic_vector(0 to 3) := (others => '0')
  );
end entity;

architecture a of syntax_highlight_test2 is

  signal clk : std_ulogic := '0';

begin

  my_block : block
    constant my_constant : positive := 1;
  begin

    status : process
    begin
      wait until rising_edge(clk);
    end process;

    dummy : process
    begin
      wait until rising_edge(clk);
    end process;

    process
    begin
      wait until rising_edge(clk);
    end process;
  end block;

end architecture;

[bpadalino]

I don't think you were using #66. It turned out that the scoping was incorrect and you would have seen nothing highlighted on the screen with #66. Same with #68.

Can you please retry and see if you get better results? Note you will need to replace the vhdl.tmLanguage file.

[LukasVik]

Yes it seems this is not a problem with #66. And I did indeed build from the wrong commit. Closing this issue.