Update for_loop_limitation.md

[WorldofKerry]

Closes #144

[WorldofKerry]

1. Is the generated FSM for the caller?

I've removed caller and callee from the doc to avoid confusion.

2. Why can't Work then Loop be under the Loop state?

Because work may take more than one cycle to complete.

3. Where are your function calls?

I forgot to change the title. This is about for loops.

4. Are the done, valid signals from the callee?

the done and valid signals are from the generator instance (so you can think of it as the callee)

5. For the flag solution, what's the difference between is_done and done?

is_done is the fsm caching the value of done.

@Haxrox

Hopefully this helps.

[Haxrox]

The flag solution seems the best. However, why does the FSM need to cache done? Shouldn't the module hold done until start is asserted? Alternatively, you could use the "ready" signal to indicate the generator is done yielding values

[WorldofKerry]

The flag solution seems the best. However, why does the FSM need to cache done? Shouldn't the module hold done until start is asserted?

Didn't we go through this before? If the module holds done, then it can't "undone" quick enough.

Alternatively, you could use the "ready" signal to indicate the generator is done yielding values

ready is an input to the module.

[Haxrox]

I think the module can hold done for more than one clk cycle. Our discussion yesterday was because an output relied on the current state it was in, which is why done could only survive with one clk cycle.