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Xilinx / Vitis-AI

Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.
https://www.xilinx.com/ai
Apache License 2.0
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ERROR: [VPL 60-1328] Vpl run 'vpl' failed #1467

Open a42385029 opened 1 week ago

a42385029 commented 1 week ago

in Vitis can't build project: ERROR: [VPL 60-1328] Vpl run 'vpl' failed WARNING: [VPL 60-1142] Unable to read data from '/home/zhr/Project/dpu_vitis1/alinx_9eg_system_hw_link/Hardware/dpu.build/link/vivado/vpl/output/generated_reports.log', generated reports will not be copied. ERROR: [VPL 60-806] Failed to finish platform linker INFO: [v++ 60-1442] [16:09:25] Run run_link: Step vpl: Failed Time (s): cpu = 00:01:07 ; elapsed = 00:01:49 . Memory (MB): peak = 458.723 ; gain = 0.000 ; free physical = 1036 ; free virtual = 1411 ERROR: [v++ 60-661] v++ link run 'run_link' failed ERROR: [v++ 60-626] Kernel link failed to complete ERROR: [v++ 60-703] Failed to finish linking INFO: [v++ 60-1653] Closing dispatch client. make: *** [makefile:58: dpu.xclbin] Error 1

a42385029 commented 6 days ago

source vpl.tcl -notrace INFO: Dispatch client connection id - 44177 [21:01:58] Run vpl: Step create_project: Started INFO: [OCL_UTIL] current step: vpl.create_project Creating Vivado project. INFO: [OCL_UTIL] set ::origin_dir_loc .local/hw_platform/prj INFO: [OCL_UTIL] set ::user_project_name prj INFO: [OCL_UTIL] internal step: source .local/hw_platform/prj/rebuild.tcl to create prj project INFO: [Project 1-1727] Source BDs should be added before importing the top BD /home/zhr/Project/dpu_vitis3/dpu_alinx_system_hw_link/Hardware/dpu.build/link/vivado/vpl/.local/hw_platform/prj/dpu_test.srcs/sources_1/bd/design_1/design_1.bd with BDC INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/zhr/Xilinx/Vivado/2022.2/data/ip'. ERROR: caught error: ERROR: [Common 17-69] Command failed: File '/home/zhr/Project/dpu_vitis3/dpu_alinx_system_hw_link/Hardware/dpu.build/link/vivado/vpl/prj/dpu_test.srcs/utils_1/imports/synth_1/design_1_wrapper.dcp' does not exist

while executing

"rdi::set_property -name incremental_checkpoint -value /home/zhr/Project/dpu_vitis3/dpu_alinx_system_hw_link/Hardware/dpu.build/link/vivado/vpl/prj/dpu..." invoked from within "set_property -name "incremental_checkpoint" -value "$proj_dir/dpu_test.srcs/utils_1/imports/synth_1/design_1_wrapper.dcp" -objects $obj" (file ".local/hw_platform/prj/rebuild.tcl" line 262) invoked from within "source $hw_platform_rebuild_tcl" [21:02:02] Run vpl: Step create_project: Failed INFO: [OCL_UTIL] current step: vpl.create_project failed. To rerun the existing project please use --from_step vpl.create_project Failed to rebuild a project required for hardware synthesis. The project is 'prj'. The rebuild script is '.local/hw_platform/prj/rebuild.tcl'. The rebuild script was delivered as part of the hardware platform. Consult with the hardware platform provider to investigate the rebuild script contents. An error stack with function names and arguments may be available in the 'vivado.log'. INFO: [Common 17-206] Exiting Vivado at Sat Sep 21 21:02:02 2024...