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Xilinx / Vitis_Libraries

Vitis Libraries
https://docs.xilinx.com/r/en-US/Vitis_Libraries
Apache License 2.0
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Data compression kernel with data width > 8 bits? #185

Open fandahao17 opened 1 year ago

fandahao17 commented 1 year ago

Hi there,

In our application the stream data width is 128 bit. However, we found that all data compression kernels here seems to have a fixed data width of 8 bits. This means the data compression rate can not keep up with data transmission rate.

I wonder why you chose to use a low data width here. Are there ant technical constraints (e.g., memory size)?

Thanks!