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Xilinx / XilinxVirtualCable

Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and provides a means to access and debug your FPGA or SoC design without using a physical cable.
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About JTAG mux or bridge to enable multiple target FPGA connections #3

Open caomxin opened 6 years ago

caomxin commented 6 years ago

Hi, recently I'm on a project to connect multiple Target FPGAs to a Microzed 7010 motherboard. I have successfully implemented One Single daughter board following "XAPP1251 (v1.0) April 30, 2015". However that implementation limit the JTAG signals to only PMOD JA and I want to do some multiplexing work. I have read JTAG SCAN BRIDGE and many other relevant materials but have no idea how to get it work.

My idea is to share TCK, TMS for JA, JB, JC etc and TDI for JA and TDO for the last PMOD that pinned together. Will that work? Thanks.

adrianh-xlnx commented 6 years ago

Have you considered creating a JTAG chain with your devices as shown below?

JA -> JB -> JC

If you create a chain you won't need a scan bridge and the Vivado tools should work with no problems; provided all the devices follow the ieee 1149.1a spec.

adrianh-xlnx commented 6 years ago

Sorry, for accidentally closing the thread.... pressed wrong button.

Here is one link that you can see on page 10 how the devices are wired up:

https://www.corelis.com/education/JTAG-Tutorial.pdf

Hope this helps.

prshant-mehta commented 7 months ago

@caomxin - Can we close this issue if @adrianh-xlnx's response answers your question?