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Xilinx / xup_vitis_network_example

VNx: Vitis Network Examples
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In branch `host_xrt`, the tx end can send the packets but the rx end keeps waiting. #109

Closed zhangchenqi123 closed 1 year ago

zhangchenqi123 commented 1 year ago

First I run the rx end: image Then I run the tx end: image But the rx end is still waiting: image

On the tx end，I used vnx_basic_if0.xclbin,On the rx end, I used vnx_basic_if1.xclbin. I have also tried to use vnx_basic_if3.xclbin on both tx end and rx end, but the results are the same: The rx end keeps waiting.

Two Alveo U280 FPGAs on two servers. The two FPGAs are directly connected. I have successfully run the vnx-benchmark-throughput.ipynb. It shows the two FPGAs can send packets to each other.

Environment:

The OS of the two servers are  Ubuntu 18.04 and Ubuntu 20.04

The following version is the same on both servers：
Platform:  xilinx_u280_gen3x16_xdma_1_202211_1
Vitis: 2022.2
XRT Version:  2.14.354

Do you know the possible reason for this? I would appreciate any help you may provide.

mariodruiz commented 1 year ago

Hi @zhangchenqi123,

The branch you are referring to it is not longer supported. There are C++ APIs in the master branch.