Xilinx / xup_vitis_network_example

VNx: Vitis Network Examples
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Compiler error with Alveo xilinx_u50_gen3x16_xdma_5_202210_1 with Vivado and Vitis Version 2023.1 and XRT xrt_202310.2.15.225_20.04-amd64-xrt #121

Closed lizajoseph closed 9 months ago

lizajoseph commented 9 months ago

For Vivado questions, please use Vivado forum ERROR: [VPL 8-11365] for the instance 'network_layer_bd_i' of module 'network_layer_bd' declared at /xup_vitis_network_example/basic.intf0.xilinx_u50_gen3x16_xdma_5_202210_1/link/vivado/vpl/prj/prj.gen/my_rm/bd/ulp/ipshared/b30f/src/network_layer_bd.v:13' ERROR: [VPL 8-11365] for the instance 'network_layer_bd_i' of module 'network_layer_bd' declared at

For Vitis questions, please use the Vitis forum

For Vitis questions, please use the Vitis forum

For pynq questions, please use the PYNQ discussion forum.

Usign Vitis 2021.2 or older? Make sure the Y2K22 patch is applied

If you still want to raise an issue here, please give us as much detail as possible to the issue you are seeing. We have listed some helpful fields below.

Build Issues

  1. OS version, e.g. lsb_release -a
  2. Vitis version vitis -version
    1. If Vitis is 2021.2 or older. Is the Y2K22 patch applied?
  3. XRT version xbutil version

Run Time Issues

  1. OS version lsb_release -a
  2. XRT version xbutil version
  3. pynq version pynq version
  4. JupyterLab and Dask version if applicable
lizajoseph commented 9 months ago

Even after sourcing the Vitis and Vivado 2023.1 settings64.sh and XRT xrt_202310.2.15 getting below compile error for Alveo xilinx_u50_gen3x16_xdma_5_202210_1 ERROR: [VPL 8-11365] for the instance 'network_layer_bd_i' of module 'network_layer_bd' declared at '/home/liza.joseph@CORP.FLOWEDGE.IN/XUP_Vitis_Network_example/xup_vitis_network_example/basic.intf0.xilinx_u50_gen3x16_xdma_5_202210_1/link/vivado/vpl/prj/prj.gen/my_rm/bd/ulp/ipshared/b30f/src/network_layer_bd.v:13', named port connection 'ap_clk' does not exist [/home/liza.joseph@CORP.FLOWEDGE.IN/XUP_Vitis_Network_example/xup_vitis_network_example/basic.intf0.xilinx_u50_gen3x16_xdma_5_202210_1/link/vivado/vpl/prj/prj.gen/my_rm/bd/ulp/ipshared/b30f/src/networklayer.v:99]

mariodruiz commented 9 months ago

Hi @lizajoseph,

Please provide this information

Build Issues

  1. OS version, e.g. lsb_release -a
  2. Vitis version vitis -version
  3. XRT version xbutil version

Also, what design are you trying to build? Please, provide the full command

lizajoseph commented 9 months ago

1) OS version - Ubuntu 20.04 2) Vitis version - 2023.1 3) XRT version - 2.15.225

I am trying to build the basic design for Alveo xilinx_u50_gen3x16_xdma_5_202210_1

Command to run the basic XUP vitis example make all DEVICE=xilinx_u50_gen3x16_xdma_5_202210_1 INTERFACE=0 DESIGN=basic

mariodruiz commented 9 months ago

I was able to generate the design from a fresh copy of the repo without problems.

Can you please try that?

make all DEVICE=xilinx_u50_gen3x16_xdma_5_202210_1.xpfm DESIGN=basic 2>&1 | tee build.log

If it does not work, please share the build.log

lizajoseph commented 9 months ago

With a fresh repo copy and with the command you have shared, I am able to generate the .xclbin

make all DEVICE=xilinx_u50_gen3x16_xdma_5_202210_1.xpfm DESIGN=basic 2>&1 | tee build.log

mariodruiz commented 9 months ago

Resolved