Closed lizajoseph closed 9 months ago
Even after sourcing the Vitis and Vivado 2023.1 settings64.sh and XRT xrt_202310.2.15 getting below compile error for Alveo xilinx_u50_gen3x16_xdma_5_202210_1 ERROR: [VPL 8-11365] for the instance 'network_layer_bd_i' of module 'network_layer_bd' declared at '/home/liza.joseph@CORP.FLOWEDGE.IN/XUP_Vitis_Network_example/xup_vitis_network_example/basic.intf0.xilinx_u50_gen3x16_xdma_5_202210_1/link/vivado/vpl/prj/prj.gen/my_rm/bd/ulp/ipshared/b30f/src/network_layer_bd.v:13', named port connection 'ap_clk' does not exist [/home/liza.joseph@CORP.FLOWEDGE.IN/XUP_Vitis_Network_example/xup_vitis_network_example/basic.intf0.xilinx_u50_gen3x16_xdma_5_202210_1/link/vivado/vpl/prj/prj.gen/my_rm/bd/ulp/ipshared/b30f/src/networklayer.v:99]
Hi @lizajoseph,
Please provide this information
Also, what design are you trying to build? Please, provide the full command
1) OS version - Ubuntu 20.04 2) Vitis version - 2023.1 3) XRT version - 2.15.225
I am trying to build the basic design for Alveo xilinx_u50_gen3x16_xdma_5_202210_1
Command to run the basic XUP vitis example make all DEVICE=xilinx_u50_gen3x16_xdma_5_202210_1 INTERFACE=0 DESIGN=basic
I was able to generate the design from a fresh copy of the repo without problems.
Can you please try that?
make all DEVICE=xilinx_u50_gen3x16_xdma_5_202210_1.xpfm DESIGN=basic 2>&1 | tee build.log
If it does not work, please share the build.log
With a fresh repo copy and with the command you have shared, I am able to generate the .xclbin
make all DEVICE=xilinx_u50_gen3x16_xdma_5_202210_1.xpfm DESIGN=basic 2>&1 | tee build.log
Resolved
For Vivado questions, please use Vivado forum ERROR: [VPL 8-11365] for the instance 'network_layer_bd_i' of module 'network_layer_bd' declared at /xup_vitis_network_example/basic.intf0.xilinx_u50_gen3x16_xdma_5_202210_1/link/vivado/vpl/prj/prj.gen/my_rm/bd/ulp/ipshared/b30f/src/network_layer_bd.v:13' ERROR: [VPL 8-11365] for the instance 'network_layer_bd_i' of module 'network_layer_bd' declared at
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