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Xilinx / xup_vitis_network_example

VNx: Vitis Network Examples
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How to test the PCIe bandwidth in the benchmark design? #91

Closed IskandarZhang closed 2 years ago

IskandarZhang commented 2 years ago

Hi Mario, long time. I noticed that only the throughput test between Kernels is involved in the Benchmark design. How should the bandwidth between CPU and FPGA, that is, PCIe bandwidth, be tested? Thanks.

mariodruiz commented 2 years ago

Hi @IskandarZhang,

This is the same question as 1 in here https://github.com/Xilinx/xup_vitis_network_example/issues/82

This is outside the scope of this project.