YosysHQ / arachne-pnr

Place and route tool for FPGAs
MIT License
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Assertion failed: (cnet_net[cn] == nullptr || cnet_net[cn] == n), function route, file src/route.cc, line 698. #87

Closed alangarf closed 6 years ago

alangarf commented 6 years ago

Weird issue I found, and I've broken it down to the minimum Verilog to demonstrate it. Not at all advocating this chunk of Verilog is any good. I'm using the iCE40HX8K evaluation board, and was attempting to use the 6502 softcore from http://www.aholme.co.uk/6502/Main.htm. I was using the start up counter without the Xilinx DCM stuff and I discovered this weird bug.

The same code works in IceCube2 however using yosys and arachne-pnr I always get this assert. Here is a small demonstration of what I'm seeing.

module top (
    input clk,
    output res
);

    reg [7:0] start;
    always @ (posedge clk)
        if (~start[7]) start <= start + 1;
    assign res = start[7];

endmodule
# For the iCE40HX-8K Breakout Board

## System Clock
set_io clk J3

### LEDs
set_io res B5
$ yosys -V
Yosys 0.7 (git sha1 UNKNOWN, clang 9.0.0 -fPIC -Os)
$arachne-pnr -v
arachne-pnr 0.1+252+ 0 (git sha1 a32dd2c, c++ 9.0.0 -O2)

$ yosys -q -p "synth_ice40 -blif test.blif" *.v
$ arachne-pnr -d 8k -P ct256 -o basic.asc -p ice40hx8k.pcf test.blif
seed: 1
device: 8k
read_chipdb +/share/arachne-pnr/chipdb-8k.bin...
  supported packages: cb132, cb132:4k, cm121, cm121:4k, cm225, cm225:4k, cm81, cm81:4k, ct256, tq144:4k
read_blif test.blif...
prune...
read_pcf ice40hx8k.pcf...
instantiate_io...
pack...

After packing:
IOs          2 / 206
GBs          0 / 8
  GB_IOs     0 / 8
LCs          12 / 7680
  DFF        3
  CARRY      2
  CARRY, DFF 5
  DFF PASS   0
  CARRY PASS 1
BRAMs        0 / 32
WARMBOOTs    0 / 1
PLLs         0 / 2

place_constraints...
promote_globals...
  promoted clk$2, 8 / 8
  promoted $abc$200$n3, 6 / 6
  promoted 2 nets
    1 cen/wclke
    1 clk
  2 globals
    1 cen/wclke
    1 clk
realize_constants...
  realized 1
place...
  initial wire length = 293
  at iteration #50: temp = 11.3403, wire length = 117
  at iteration #100: temp = 4.99118, wire length = 106
  at iteration #150: temp = 1.53407, wire length = 50
  at iteration #200: temp = 0.0054219, wire length = 41
  final wire length = 41

After placement:
PIOs       3 / 206
PLBs       4 / 960
BRAMs      0 / 32

  place time 0.01s
route...
n $true cn 4055 cnet_net[cn] $abc$200$n3$2
Assertion failed: (cnet_net[cn] == nullptr || cnet_net[cn] == n), function route, file src/route.cc, line 698.
Abort trap: 6

Changing this chunk of "start" code to something better has removed the assert trigging, but I'm unsure what's actually causing it. I've tried to dig into the code to see if I can help, but I quickly fell out of my depth. Any assistance or explanation of what is wrong with this would be greatly appreciated. Thanks!

cliffordwolf commented 6 years ago

I think this is a duplicate of #65.