Weird issue I found, and I've broken it down to the minimum Verilog to demonstrate it. Not at all advocating this chunk of Verilog is any good. I'm using the iCE40HX8K evaluation board, and was attempting to use the 6502 softcore from http://www.aholme.co.uk/6502/Main.htm. I was using the start up counter without the Xilinx DCM stuff and I discovered this weird bug.
The same code works in IceCube2 however using yosys and arachne-pnr I always get this assert. Here is a small demonstration of what I'm seeing.
module top (
input clk,
output res
);
reg [7:0] start;
always @ (posedge clk)
if (~start[7]) start <= start + 1;
assign res = start[7];
endmodule
# For the iCE40HX-8K Breakout Board
## System Clock
set_io clk J3
### LEDs
set_io res B5
Changing this chunk of "start" code to something better has removed the assert trigging, but I'm unsure what's actually causing it. I've tried to dig into the code to see if I can help, but I quickly fell out of my depth. Any assistance or explanation of what is wrong with this would be greatly appreciated. Thanks!
Weird issue I found, and I've broken it down to the minimum Verilog to demonstrate it. Not at all advocating this chunk of Verilog is any good. I'm using the iCE40HX8K evaluation board, and was attempting to use the 6502 softcore from http://www.aholme.co.uk/6502/Main.htm. I was using the start up counter without the Xilinx DCM stuff and I discovered this weird bug.
The same code works in IceCube2 however using yosys and arachne-pnr I always get this assert. Here is a small demonstration of what I'm seeing.
Changing this chunk of "start" code to something better has removed the assert trigging, but I'm unsure what's actually causing it. I've tried to dig into the code to see if I can help, but I quickly fell out of my depth. Any assistance or explanation of what is wrong with this would be greatly appreciated. Thanks!