YosysHQ / icestorm

Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
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icebox_vlog: improve module declaration and unit testing #329

Open X-Illuminati opened 2 months ago

X-Illuminati commented 2 months ago

Resolves #328

First commit changes iceblox_vlog to output Verilog-2001 module declarations by default. An additional command line option (-C) supports output of Verilog-1995 module declarations for backwards compatibility.

Second commit adds test cases that try out different combinations of commandline options for iceblox_vlog and ensure they parse correctly with iverilog and yosys. I didn't see any other obvious regression tests, so I added these to support development in the future.

X-Illuminati commented 2 months ago

It seems clear to me that icebox_vlog is largely superceded by the yosys "write_verilog" command. This change may be seen mostly as a personal journey in understanding, but it may prove useful for continuing to work with unmaintained scripts in other projects.

X-Illuminati commented 2 months ago

@gatecat I hope you can review this or assign to a relevant reviewer.