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Yosys Open SYnthesis Suite
https://yosyshq.net/yosys/
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$not cell optimized away/not present in synthesized result #2407

Closed arjenroodselaar closed 4 years ago

arjenroodselaar commented 4 years ago

Steps to reproduce the issue

I am using Yosys to model a small circuit with some discrete parts. In the attached zip file this circuit is found in aux_bus.v, with blackbox parts in serdes. When running the Yosys script and examine the output it appears the "not" cell in the cmd_stb signal is not present. The intention of this bit of logic is for cmd_stb to be high when lock_n, rx_word[0] and rclk are low, which is not what is represented in the synthesized output. I tried to use either the ~ or ! operators. Using these operators on the internal signals works as expected. What am I missing? I went through the truth table by hand and can't see this being a valid optimization. Am I holding the tool wrong?

aux_bus.zip Screen Shot 2020-10-21 at 2 28 58 PM

This is on a Yosys build from a few nights ago: Yosys 0.9+3627 (open-tool-forge build) (git sha1 06347b11, clang 11.0.3 ).

Expected behavior

I would expect to see a $not cell after cell $6 before being connected to the CLK of the $dff.

Actual behavior

The $not cell is omitted in the synthesized output, causing the $dff to be clocked when any of the input signals is high.

arjenroodselaar commented 4 years ago

It seems I am holding the tool wrong in this case. Replacing the 'prep' command with explicit synthesis steps and passing -noclkinv to the opt steps does what I expected. Apologies for opening this.